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Zhiping Yu: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. C. K. Cheng, Steve Lin, Andrew B. Kahng, Keh-Jeng Chang, Vijay Pitchumani, Toshiyuki Shibuya, Roberto Suaya, Zhiping Yu, Fook-Luen Heng, Don MacMillen
    Panel I: who is responsible for the design for manufacturability issues in the era of nano-technologies? [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:- [Conf]
  2. Zuochang Ye, Zhiping Yu
    Parasitics extraction involving 3-D conductors based on multi-layered Green's function. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:689-693 [Conf]
  3. Lifeng Wu, Zhilian Yang, Zhiping Yu, Zhijian Li
    GOALSERVER: A Multiobjective Design Optimization Tool for IC Fabrication Process. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:585-590 [Conf]
  4. Zhiping Yu, Weijian Zhao, Zhilian Yang, Y. Edmund Lien
    A Novel Algorithm for Improving Convergence Behavior of Circuit Simulators. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:626-629 [Conf]
  5. Tao Li, Ximeng Guan, Zhiping Yu, Wei Xue
    Computation of Si Nanowire Bandstructures on Parallel Machines Through Domain Decomposition. [Citation Graph (0, 0)][DBLP]
    International Conference on Computational Science (1), 2006, pp:250-257 [Conf]
  6. Boris Troyanovsky, Zhiping Yu, Lydia So, Robert W. Dutton
    Relaxation-based harmonic balance technique for semiconductor device simulation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:700-703 [Conf]
  7. Zihong Liu, Zhihua Wang, GuoLin Li, Zhiping Yu
    A Novel Solid Neuron-Network Chip Based on Both Biological and Artificial Neural Network Theories. [Citation Graph (0, 0)][DBLP]
    ISNN (1), 2005, pp:479-484 [Conf]
  8. Hai Lan, Zhiping Yu, Robert W. Dutton
    A CAD-Oriented Modeling Approach of Frequency-Dependent Behavior of Substrate Noise Coupling for Mixed-Signal IC Design. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:195-0 [Conf]
  9. Tae-young Oh, Zhiping Yu, Robert W. Dutton
    AC Analysis of Thin Gate Oxide MOS with Quantum Mechanical Corrections. [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:326-330 [Conf]
  10. Zhiping Yu, Dan Yergeau, Robert W. Dutton, Sam Nakagawa, Norman Chang, Shen Lin, Weize Xie
    Full Chip Thermal Simulation. [Citation Graph (0, 0)][DBLP]
    ISQED, 2000, pp:145-150 [Conf]
  11. Gaofeng Wang, Xiaoning Qi, Zhiping Yu, Robert W. Dutton
    Accurate Model of Metal-Insulator-Semiconductor Interconnects. [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:48-52 [Conf]
  12. Datong Chen, Satoshi Sugino, Zhiping Yu, Robert W. Dutton
    Modeling of the charge balance condition on floating gates and simulation of EEPROMs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:10, pp:1499-1502 [Journal]
  13. Ronald J. G. Goossens, Stephen G. Beebe, Zhiping Yu, Robert W. Dutton
    An automatic biasing scheme for tracing arbitrarily shaped I-V curves. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:3, pp:310-317 [Journal]
  14. Yutao Ma, Litian Liu, Lilin Tian, Zhiping Yu, Zhijian Li
    Analytical charge-control and I-V model for submicrometer anddeep-submicrometer MOSFETs fully comprising quantum mechanical effects. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:4, pp:495-502 [Journal]
  15. Chiaki Takano, Zhiping Yu, Robert W. Dutton
    A nonequilibrium one-dimensional quantum-mechanical simulation for AlGaAs/GaAs HEMT structures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:11, pp:1217-1224 [Journal]
  16. Zhiping Yu, Robert W. Dutton, Massimo Vanzi
    An Extension to Newton's Method in Device Simulators--On An Efficient Algorithm to Evaluate Small-Signal Parameters and to Predict Initial Guess. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:1, pp:41-45 [Journal]
  17. Tao Li, Zhiping Yu
    Statistical Analysis of Full-Chip Leakage Power Considering Junction Tunneling Leakage. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:99-102 [Conf]

  18. Massively Parallel Finite Element Simulator for Full-Chip STI Stress Analysis. [Citation Graph (, )][DBLP]

  19. Efficient techniques for 3-D impedance extraction using mixed boundary element method. [Citation Graph (, )][DBLP]

  20. Full-chip leakage analysis in nano-scale technologies: mechanisms, variation sources, and verification. [Citation Graph (, )][DBLP]

  21. Efficient tail estimation for massive correlated log-normal sums: with applications in statistical leakage analysis. [Citation Graph (, )][DBLP]

  22. An Efficient Method for Chip-Level Statistical Capacitance Extraction Considering Process Variations with Spatial Correlation. [Citation Graph (, )][DBLP]

  23. A highly efficient optimization algorithm for pixel manipulation in inverse lithography technique. [Citation Graph (, )][DBLP]

  24. An efficient algorithm for modeling spatially-correlated process variation in statistical full-chip leakage analysis. [Citation Graph (, )][DBLP]

  25. Layout-dependent STI stress analysis and stress-aware RF/analog circuit design optimization. [Citation Graph (, )][DBLP]

  26. A Statistical Characterization of CMOS Process Fluctuations in Subthreshold Current Mirrors. [Citation Graph (, )][DBLP]

  27. Full-Chip Leakage Verification for Manufacturing Considering Process Variations. [Citation Graph (, )][DBLP]

  28. A comprehensive model for gate delay under process variation and different driving and loading conditions. [Citation Graph (, )][DBLP]

  29. High performance source optimization using a gradient-based method in optical lithography. [Citation Graph (, )][DBLP]

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