The SCEAS System
Navigation Menu

Search the dblp DataBase


Fook-Luen Heng: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. C. K. Cheng, Steve Lin, Andrew B. Kahng, Keh-Jeng Chang, Vijay Pitchumani, Toshiyuki Shibuya, Roberto Suaya, Zhiping Yu, Fook-Luen Heng, Don MacMillen
    Panel I: who is responsible for the design for manufacturability issues in the era of nano-technologies? [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:- [Conf]
  2. Puneet Gupta, Fook-Luen Heng
    Toward a systematic-variation aware timing methodology. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:321-326 [Conf]
  3. Lars Liebmann, Jennifer Lund, Fook-Luen Heng, Ioana Graur
    Enabling Alternating Phase Shifted Mask Designs for a Full Logic Gate Level: Design Rules and Design Rule Checking. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:79-84 [Conf]
  4. Zhan Chen, Fook-Luen Heng
    A Fast Minimum Layout Perturbation Algorithm for Electromigration Reliability Enhancement. [Citation Graph (0, 0)][DBLP]
    DFT, 1998, pp:56-63 [Conf]
  5. Alexey Lvov, Fook-Luen Heng
    A graph based simplex method for the integer minimum perturbation problem with sum and difference constraints. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:67-72 [Conf]
  6. Mark A. Lavin, Fook-Luen Heng, Gregory A. Northrop
    Backend CAD flows for "restrictive design rules". [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:739-746 [Conf]
  7. Fook-Luen Heng, Zhan Chen, Gustavo E. Téllez
    A VLSI artwork legalization technique based on a new criterion of minimum layout perturbation. [Citation Graph (0, 0)][DBLP]
    ISPD, 1997, pp:116-121 [Conf]
  8. Fook-Luen Heng, Lars Liebmann, Jennifer Lund
    Application of automated design migration to alternating phase shift mask design. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:38-43 [Conf]
  9. Xin Yuan, Kevin W. McCullen, Fook-Luen Heng, Robert F. Walker, Jason Hibbeler, Robert J. Allen, Rani R. Narayan
    Technology migration technique for designs with strong RET-driven layout restrictions. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:175-182 [Conf]

  10. Yield estimation of SRAM circuits using "Virtual SRAM Fab". [Citation Graph (, )][DBLP]

  11. Pre-Si estimation and compensation of SRAM layout deficiencies to achieve target performance and yield. [Citation Graph (, )][DBLP]

Search in 0.010secs, Finished in 0.011secs
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002