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Publications of Author

1. Lerong Cheng, Xiaoyu Song, Guowu Yang, Zhiwei Tang
   A fast congestion estimator for routing with bounded detours. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2004, pp:666-670 [Conf]
   
2. Lerong Cheng, Phoebe Wong, Fei Li, Yan Lin, Lei He
   Device and architecture co-optimization for FPGA power reduction. [Citation Graph (0, 0)][DBLP]
   DAC, 2005, pp:915-920 [Conf]
   
3. Ho-Yan Wong, Lerong Cheng, Yan Lin, Lei He
   FPGA device and architecture evaluation considering process variations. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2005, pp:19-24 [Conf]
   
4. Lerong Cheng, William N. N. Hung, Guowu Yang, Xiaoyu Song
   Congestion Estimation for 3D Routing. [Citation Graph (0, 0)][DBLP]
   ISVLSI, 2004, pp:239-240 [Conf]
   
5. Fei He, Xiaoyu Song, Lerong Cheng, Guowu Yang, Zhiwei Tang, Ming Gu, Jia-Guang Sun
   A Hierachical Method for Wiring and Congestion Prediction. [Citation Graph (0, 0)][DBLP]
   ISVLSI, 2005, pp:307-308 [Conf]
   
6. Fei He, Ming Gu, Xiaoyu Song, Zhiwei Tang, Guowu Yang, Lerong Cheng
   Probabilistic Estimation for Routing Space. [Citation Graph (0, 0)][DBLP]
   Comput. J., 2005, v:48, n:6, pp:667-676 [Journal]
   
7. Ming Gu, Fei He, Lerong Cheng, Xiaoyu Song, Guowu Yang
   Congestion estimation for hexagonal routing. [Citation Graph (0, 0)][DBLP]
   Int. J. Comput. Math., 2006, v:83, n:3, pp:263-272 [Journal]
   
8. Fei He, Lerong Cheng, Guowu Yang, Xiaoyu Song, Ming Gu, Jia-Guang Sun
   On Theoretical Upper Bounds for Routing Estimation. [Citation Graph (0, 0)][DBLP]
   J. UCS, 2005, v:11, n:6, pp:916-925 [Journal]
   
9. William N. N. Hung, Xiaoyu Song, T. Kam, Lerong Cheng, Guowu Yang
   Routability checking for three-dimensional architectures. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2004, v:12, n:12, pp:1371-1374 [Journal]
   
10. Lerong Cheng, Jinjun Xiong, Lei He
    Non-Linear Statistical Static Timing Analysis for Non-Gaussian Variation Sources. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:250-255 [Conf]
    
11. Lerong Cheng, Jinjun Xiong, Lei He, Mike Hutton
    FPGA Performance Optimization Via Chipwise Placement Considering Process Variations. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
    
12. 
    Accounting for non-linear dependence using function driven component analysis. [Citation Graph (, )][DBLP]
    
    
13. 
    Non-Gaussian statistical timing analysis using second-order polynomial fitting. [Citation Graph (, )][DBLP]
    
    
14. 
    Physically justifiable die-level modeling of spatial variation in view of systematic across wafer variability. [Citation Graph (, )][DBLP]
    
    
15. 
    Trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability. [Citation Graph (, )][DBLP]