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Sri Parameswaran: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Newton Cheung, Sri Parameswaran, Jörg Henkel
    Battery-aware instruction generation for embedded processors. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:553-556 [Conf]
  2. Hui Guo, Sri Parameswaran
    Unrolling Loops With Indeterminate Loop Counts in System Level Pipelines. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:99-104 [Conf]
  3. Tony Han, Sri Parameswaran
    Swasad: An Asic Design For High Speed Dna Sequence Matching. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:541-546 [Conf]
  4. Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran
    A novel instruction scratchpad memory optimization method based on concomitance metric. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:612-617 [Conf]
  5. Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran
    Finding optimal L1 cache configuration for embedded systems. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:796-801 [Conf]
  6. Pradip K. Jha, Nikil D. Dutt, Sri Parameswaran
    Reclocking for high-level synthesis. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  7. Allan Rae, Sri Parameswaran
    Voltage reduction of application-specific heterogeneous multiprocessor systems for power minimisation. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:147-152 [Conf]
  8. Sri Parameswaran
    HW-SW Co-Synthesis: The Present and The Future (Embedded Tutorial). [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:19-22 [Conf]
  9. Sri Parameswaran, Hui Guo
    Power Reduction in Pipelines. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:545-550 [Conf]
  10. Roshan G. Ragel, Sri Parameswaran, Sayed Mohammad Kia
    Micro embedded monitoring for security in application specific instruction-set processors. [Citation Graph (0, 0)][DBLP]
    CASES, 2005, pp:304-314 [Conf]
  11. Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran
    Dual-pipeline heterogeneous ASIP design. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:12-17 [Conf]
  12. Seng Lin Shee, Sri Parameswaran, Newton Cheung
    Novel architecture for loop acceleration: a case study. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2005, pp:297-302 [Conf]
  13. Roshan G. Ragel, Sri Parameswaran
    Hardware assisted pre-emptive control flow checking for embedded processors to improve reliability. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:100-105 [Conf]
  14. Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran, Aleksandar Ignjatovic
    Application specific forwarding network and instruction encoding for multi-pipe ASIPs. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:241-246 [Conf]
  15. Seng Lin Shee, Andrea Erdos, Sri Parameswaran
    Heterogeneous multiprocessor implementations for JPEG: : a case study. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:217-222 [Conf]
  16. V. E. Boros, Aleksandar D. Rakic, Sri Parameswaran
    High-level model of a WDMA passive optical bus for a reconfigurable multiprocessor system. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:221-226 [Conf]
  17. Roshan G. Ragel, Sri Parameswaran
    IMPRES: integrated monitoring for processor reliability and security. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:502-505 [Conf]
  18. Newton Cheung, Jörg Henkel, Sri Parameswaran
    Rapid Configuration and Instruction Selection for an ASIP: A Case Study. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10802-10809 [Conf]
  19. Newton Cheung, Sri Parameswaran, Jörg Henkel, Jeremy Chan
    MINCE: Matching INstructions Using Combinational Equivalence for Extensible Processor. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1020-1027 [Conf]
  20. Sri Parameswaran
    Code placement in hardware/software co-synthesis to improve performance and reduce cost. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:626-632 [Conf]
  21. Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran
    Customization of application specific heterogeneous multi-pipeline processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:746-751 [Conf]
  22. Jeremy Chan, Sri Parameswaran
    NoCEE: energy macro-model extraction methodology for network on chip routers. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:254-259 [Conf]
  23. Newton Cheung, Sri Parameswaran, Jörg Henkel
    INSIDE: INstruction Selection/Identification & Design Exploration for Extensible Processors. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:291-298 [Conf]
  24. Newton Cheung, Sri Parameswaran, Jörg Henkel
    A quantitative study and estimation models for extensible instructions in embedded processors. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:183-189 [Conf]
  25. Andhi Janapsatya, Sri Parameswaran, Aleksandar Ignjatovic
    Hardware/software managed scratchpad memory for embedded system. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:370-377 [Conf]
  26. Sri Parameswaran, Jörg Henkel
    I-CoPES: Fast Instruction Code Placement for Embedded Systems to Improve Performance and Energy Efficiency. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:635-0 [Conf]
  27. Matthew F. Parkinson, Sri Parameswaran
    Profiling in the ASP codesign environment. [Citation Graph (0, 0)][DBLP]
    ISSS, 1995, pp:128-133 [Conf]
  28. Allan Rae, Sri Parameswaran
    Application-Specific Heterogeneous Multiprocessor Synthesis Using Differential-Evolution. [Citation Graph (0, 0)][DBLP]
    ISSS, 1998, pp:83-88 [Conf]
  29. Hui Guo, Sri Parameswaran
    Balancing System Level Pipelines with Stage Voltage Scaling. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:287-289 [Conf]
  30. Jeremy Chan, Sri Parameswaran
    NoCGEN: A Template Based Reuse Methodology for Networks on Chip Architecture. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:717-720 [Conf]
  31. Ramesh Chandra, Preeti Ranjan Panda, Jörg Henkel, Sri Parameswaran, Loganath Ramachandran
    Specification and Design of Multi-Million Gate SOCs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:18-19 [Conf]
  32. Tony Han, Sri Parameswaran
    SWASAD: An ASIC Design for High Speed DNA Sequence Matching. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:541-546 [Conf]
  33. Ivan Siu-Chuang Lu, Neil Weste, Sri Parameswaran
    ADC Precision Requirement for Digital Ultra-Wideband Receivers with Sublinear Front-Ends: A Power and Performance Perspective. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:575-580 [Conf]
  34. Jorgen Peddersen, Seng Lin Shee, Andhi Janapsatya, Sri Parameswaran
    Rapid Embedded Hardware/Software System Generation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:111-116 [Conf]
  35. Jorgen Peddersen, Sri Parameswaran
    Energy Driven Application SelfAdaptation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:385-390 [Conf]
  36. Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran
    Exploiting statistical information for implementation of instruction scratchpad memory in embedded system. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:8, pp:816-829 [Journal]
  37. Jude Angelo Ambrose, Roshan G. Ragel, Sri Parameswaran
    RIJID: Random Code Injection to Mask Power Analysis based Side Channel Attacks. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:489-492 [Conf]
  38. Seng Lin Shee, Sri Parameswaran
    Design Methodology for Pipelined Heterogeneous Multiprocessor System. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:811-816 [Conf]
  39. Yee Jern Chong, Sri Parameswaran
    Automatic application specific floating-point unit generation. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:461-466 [Conf]
  40. Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran, Jörg Henkel
    Instruction trace compression for rapid instruction cache simulation. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:803-808 [Conf]

  41. HitME: low power Hit MEmory buffer for embedded systems. [Citation Graph (, )][DBLP]

  42. CLIPPER: Counter-based Low Impact Processor Power Estimation at Run-time. [Citation Graph (, )][DBLP]

  43. NoCOUT : NoC topology generation with mixed packet-switched and point-to-point networks. [Citation Graph (, )][DBLP]

  44. A smart random code injection to mask power analysis based side channel attacks. [Citation Graph (, )][DBLP]

  45. Synthesis of heterogeneous pipelined multiprocessor systems using ILP: jpeg case study. [Citation Graph (, )][DBLP]

  46. LOCS: a low overhead profiler-driven design flow for security of MPSoCs. [Citation Graph (, )][DBLP]

  47. LOP: a novel SRAM-based architecture for low power and high throughput packet classification. [Citation Graph (, )][DBLP]

  48. SuSeSim: a fast simulation strategy to find optimal L1 cache configuration for embedded systems. [Citation Graph (, )][DBLP]

  49. SHIELD: a software hardware design methodology for security and reliability of MPSoCs. [Citation Graph (, )][DBLP]

  50. Rapid application specific floating-point unit generation with bit-alignment. [Citation Graph (, )][DBLP]

  51. A design flow for application specific heterogeneous pipelined multiprocessor systems. [Citation Graph (, )][DBLP]

  52. SCUD: a fast single-pass L1 cache simulation approach for embedded processors with round-robin replacement policy. [Citation Graph (, )][DBLP]

  53. A Formal Approach To The Protocol Converter Problem. [Citation Graph (, )][DBLP]

  54. CUFFS: An instruction count based architectural framework for security of MPSoCs. [Citation Graph (, )][DBLP]

  55. DEW: A fast level 1 cache simulation approach for embedded processors with FIFO replacement policy. [Citation Graph (, )][DBLP]

  56. Dueling CLOCK: Adaptive cache replacement policy based on the CLOCK algorithm. [Citation Graph (, )][DBLP]

  57. Rapid runtime estimation methods for pipelined MPSoCs. [Citation Graph (, )][DBLP]

  58. Design automation of self checking circuits. [Citation Graph (, )][DBLP]

  59. Flexible multi-mode embedded floating-point unit for field programmable gate arrays. [Citation Graph (, )][DBLP]

  60. MUTE-AES: a multiprocessor architecture to prevent power analysis based side channel attack of the AES algorithm. [Citation Graph (, )][DBLP]

  61. LOP_RE: Range encoding for low power packet classification. [Citation Graph (, )][DBLP]

  62. Security and Dependability of Embedded Systems: A Computer Architects' Perspective. [Citation Graph (, )][DBLP]

  63. Anatomy of Differential Power Analysis for AES. [Citation Graph (, )][DBLP]

  64. Low-Impact Processor for Dynamic Runtime Power Management. [Citation Graph (, )][DBLP]

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