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Publications of Author

1. Hao-Yun Chin, Chao-Chung Cheng, Yu-Kun Lin, Tian-Sheuan Chang
   A bandwidth efficient subsampling-based block matching architecture for motion estimation. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2005, pp:7-8 [Conf]
   
2. Hung-Chih Lin, Yu-Jen Wang, Kai-Ting Cheng, Shang-Yu Yeh, Wei-Nien Chen, Chia-Yang Tsai, Tian-Sheuan Chang, Hsueh-Ming Hang
   Algorithms and DSP implementation of H.264/AVC. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2006, pp:742-749 [Conf]
   
3. Yu-Kun Lin, Tian-Sheuan Chang
   Fast block type decision algorithm for intra prediction in H.264 FRext. [Citation Graph (0, 0)][DBLP]
   ICIP (1), 2005, pp:585-588 [Conf]
   
4. N. Y. C. Chang, T. S. Chang
   Combined frame memory architecture for motion compensation in video decoding. [Citation Graph (0, 0)][DBLP]
   ISCAS (2), 2005, pp:1806-1809 [Conf]
   
5. Chao-Chung Cheng, Tian-Sheuan Chang
   Fast three step intra prediction algorithm for 4×4 blocks in H.264. [Citation Graph (0, 0)][DBLP]
   ISCAS (2), 2005, pp:1509-1512 [Conf]
   
6. Tian-Sheuan Chang, Chin-Sheng Kung, Chein-Wei Jen
   A simple processor core design for DCT/IDCT. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Circuits Syst. Video Techn., 2000, v:10, n:3, pp:439-447 [Journal]
   
7. Hun-Chen Chen, Jiun-In Guo, Tian-Sheuan Chang, Chein-Wei Jen
   A memory-efficient realization of cyclic convolution and its application to discrete cosine transform. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Circuits Syst. Video Techn., 2005, v:15, n:3, pp:445-453 [Journal]
   
8. Jen-Chieh Tuan, Tian-Sheuan Chang, Chein-Wei Jen
   On the data reuse and memory bandwidth analysis for full-search block-matching VLSI architecture. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Circuits Syst. Video Techn., 2002, v:12, n:1, pp:61-72 [Journal]
   
9. Yu-Jen Wang, Chao-Chung Cheng, Tian-Sheuan Chang
   A fast fractional pel motion estimation algorithm for H.264/MPEG-4 AVC. [Citation Graph (0, 0)][DBLP]
   ISCAS, 2006, pp:- [Conf]
   
10. Guo-Shiuan Yu, Tian-Sheuan Chang
    A zero-skipping multi-symbol CAVLC decoder for MPEG-4 AVC/H.264. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
    
11. Chao-Chung Cheng, Chun-Wei Ku, Tian-Sheuan Chang
    A 1280×720 pixels 30 frames/s H.264/MPEG-4 AVC intra encoder. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
    
12. 
    A 242mW, 10mm²1080p H.264/AVC high profile encoder chip. [Citation Graph (, )][DBLP]
    
    
13. 
    Real-Time DSP Implementation on Local Stereo Matching. [Citation Graph (, )][DBLP]
    
    
14. 
    Low Memory Cost Block-Based Belief Propagation for Stereo Correspondence. [Citation Graph (, )][DBLP]
    
    
15. 
    Bandwidth-rate-distortion optimized motion estimation. [Citation Graph (, )][DBLP]
    
    
16. 
    Data reuse analysis of local stereo matching. [Citation Graph (, )][DBLP]
    
    
17. 
    ISID : In-order scan and indexed diffusion segmentation algorithm for stereo vision. [Citation Graph (, )][DBLP]
    
    
18. 
    A Fast Algorithm and Its Architecture for Motion Estimation in MPEG-4 AVC/H.264 Video Coding. [Citation Graph (, )][DBLP]
    
    
19. 
    A Display Order Oriented Scalable Video Decoder. [Citation Graph (, )][DBLP]
    
    
20. 
    A Memory Bandwidth Optimized Interpolator for Motion Compensation in the H.264 Video Decoding. [Citation Graph (, )][DBLP]
    
    
21. 
    High Performance Context Adaptive Variable Length Coding Encoder for MPEG-4 AVC/H.264 Video Coding. [Citation Graph (, )][DBLP]
    
    
22. 
    Optimal Data Mapping for Motion Compensation in H.264 Video Decoding. [Citation Graph (, )][DBLP]
    
    
23. 
    SIFME: A Single Iteration Fractional-Pel Motion Estimation Algorithm and Architecture for HDTV Sized H.264 Video Coding. [Citation Graph (, )][DBLP]