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David Z. Pan: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Minsik Cho, Hongjoong Shin, David Z. Pan
    Fast substrate noise-aware floorplanning with preference directed graph for mixed-signal SOCs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:765-770 [Conf]
  2. Anand Ramalingam, Sreekumar V. Kodakara, Anirudh Devgan, David Z. Pan
    Robust analytical gate delay modeling for low voltage circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:61-66 [Conf]
  3. Anand Ramalingam, Bin Zhang, Anirudh Devgan, David Z. Pan
    Sleep transistor sizing using timing criticality and temporal currents. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1094-1097 [Conf]
  4. Sean X. Shi, David Z. Pan
    Wire sizing with scattering effect for nanoscale interconnection. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:503-508 [Conf]
  5. Gang Xu, Li-Da Huang, David Z. Pan, Martin D. F. Wong
    Redundant-via enhanced maze routing for yield improvement. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1148-1151 [Conf]
  6. Gang Xu, Ruiqi Tian, David Z. Pan, Martin D. F. Wong
    CMP aware shuttle mask floorplanning. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1111-1114 [Conf]
  7. Minsik Cho, David Z. Pan
    BoxRouter: a new global router based on box expansion and progressive ILP. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:373-378 [Conf]
  8. Tao Luo, David Newmark, David Z. Pan
    A new LP based incremental timing driven placement for high performance designs. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:1115-1120 [Conf]
  9. Ruchir Puri, Leon Stok, John M. Cohn, David S. Kung, David Z. Pan, Dennis Sylvester, Ashish Srivastava, Sarvesh H. Kulkarni
    Pushing ASIC performance in a power envelope. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:788-793 [Conf]
  10. Peng Yu, Sean X. Shi, David Z. Pan
    Process variation aware OPC with variational lithography modeling. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:785-790 [Conf]
  11. Minsik Cho, Suhail Ahmed, David Z. Pan
    TACO: temperature aware clock-tree optimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:582-587 [Conf]
  12. Anand Ramalingam, Gi-Joon Nam, Ashish Kumar Singh, Michael Orshansky, Sani R. Nassif, David Z. Pan
    An accurate sparse matrix based framework for statistical static timing analysis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:231-236 [Conf]
  13. Sean X. Shi, Peng Yu, David Z. Pan
    A unified non-rectangular device and circuit simulation model for timing and power. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:423-428 [Conf]
  14. Minsik Cho, David Z. Pan, Hua Xiang, Ruchir Puri
    Wire density driven global routing for CMP variation and timing. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:487-492 [Conf]
  15. Anand Rajaram, David Z. Pan
    Variation tolerant buffered clock network synthesis with cross links. [Citation Graph (0, 0)][DBLP]
    ISPD, 2006, pp:157-164 [Conf]
  16. Anand Rajaram, David Z. Pan, Jiang Hu
    Improved algorithms for link-based non-tree clock networks for skew variability reduction. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:55-62 [Conf]
  17. Andrew Havlir, David Z. Pan
    Simultaneous Statistical Delay and Slew Optimization for Interconnect Pipelines. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:171-178 [Conf]
  18. Anand Rajaram, David Z. Pan
    Fast Incremental Link Insertion in Clock Networks for Skew Variability Reduction. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:79-84 [Conf]
  19. Anand Ramalingam, David Z. Pan, Frank Liu, Sani R. Nassif
    Accurate Thermal Analysis Considering Nonlinear Thermal Conductivity. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:644-649 [Conf]
  20. Joon-Sung Yang, Anand Rajaram, Ninghy Shi, Jian Chen, David Z. Pan
    Sensitivity Based Link Insertion for Variation Tolerant Clock Network Synthesis. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:398-403 [Conf]
  21. Minsik Cho, David Z. Pan
    PEAKASO: Peak-Temperature Aware Scan-Vector Optimization. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:52-57 [Conf]
  22. Minsik Cho, Hua Xiang, Ruchir Puri, David Z. Pan
    TROY: Track Router with Yield-driven Wire Planning. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:55-58 [Conf]
  23. Anand Ramalingam, Ashish Kumar Singh, Sani R. Nassif, Michael Orshansky, David Z. Pan
    Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing Analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:148-153 [Conf]
  24. Gi-Joon Nam, Mehmet Can Yildiz, David Z. Pan, Patrick H. Madden
    ISPD placement contest updates and ISPD 2007 global routing contest. [Citation Graph (0, 0)][DBLP]
    ISPD, 2007, pp:167- [Conf]
  25. Anand Ramalingam, Giri Devarayanadurg, David Z. Pan
    Accurate power grid analysis with behavioral transistor network modeling. [Citation Graph (0, 0)][DBLP]
    ISPD, 2007, pp:43-50 [Conf]
  26. Anand Ramalingam, Anirudh Devgan, David Z. Pan
    Wakeup Scheduling in MTCMOS Circuits Using Successive Relaxation to Minimize Ground Bounce. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2007, v:3, n:1, pp:28-35 [Journal]

  27. Hippocrates: First-Do-No-Harm Detailed Placement. [Citation Graph (, )][DBLP]

  28. MeshWorks: An efficient framework for planning, synthesis and optimization of clock mesh networks. [Citation Graph (, )][DBLP]

  29. Total power optimization combining placement, sizing and multi-Vt through slack distribution management. [Citation Graph (, )][DBLP]

  30. DPlace2.0: A stable and efficient analytical placement based on diffusion. [Citation Graph (, )][DBLP]

  31. Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyond. [Citation Graph (, )][DBLP]

  32. ELIAD: efficient lithography aware detailed router with compact post-OPC printability prediction. [Citation Graph (, )][DBLP]

  33. Robust chip-level clock tree synthesis for SOC designs. [Citation Graph (, )][DBLP]

  34. An integrated nonlinear placement framework with congestion and porosity aware buffer planning. [Citation Graph (, )][DBLP]

  35. Double patterning lithography friendly detailed routing with redundant via consideration. [Citation Graph (, )][DBLP]

  36. An SDRAM-aware router for Networks-on-Chip. [Citation Graph (, )][DBLP]

  37. RegPlace: a high quality open-source placement framework for structured ASICs. [Citation Graph (, )][DBLP]

  38. O-Router: an optical routing framework for low power on-chip silicon nano-photonic integration. [Citation Graph (, )][DBLP]

  39. Application-aware NoC design for efficient SDRAM access. [Citation Graph (, )][DBLP]

  40. Compact modeling and robust layout optimization for contacts in deep sub-wavelength lithography. [Citation Graph (, )][DBLP]

  41. TSV stress aware timing analysis with applications to 3D-IC layout optimization. [Citation Graph (, )][DBLP]

  42. Layout Level Timing Optimization by Leveraging Active Area Dependent Mobility of Strained-Silicon Devices. [Citation Graph (, )][DBLP]

  43. Latch Modeling for Statistical Timing Analysis. [Citation Graph (, )][DBLP]

  44. Analysis and optimization of NBTI induced clock skew in gated clock trees. [Citation Graph (, )][DBLP]

  45. TIP-OPC: a new topological invariant paradigm for pixel based optical proximity correction. [Citation Graph (, )][DBLP]

  46. BoxRouter 2.0: architecture and implementation of a hybrid and robust global router. [Citation Graph (, )][DBLP]

  47. A novel intensity based optical proximity correction algorithm with speedup in lithography simulation. [Citation Graph (, )][DBLP]

  48. Overlay aware interconnect and timing variation modeling for double patterning technology. [Citation Graph (, )][DBLP]

  49. Nanolithography and CAD challenges for 32nm/22nm and beyond. [Citation Graph (, )][DBLP]

  50. Double patterning technology friendly detailed routing. [Citation Graph (, )][DBLP]

  51. Pyramids: an efficient computational geometry-based approach for timing-driven placement. [Citation Graph (, )][DBLP]

  52. A voltage-frequency island aware energy optimization framework for networks-on-chip. [Citation Graph (, )][DBLP]

  53. Partial Functional Manipulation Based Wirelength Minimization. [Citation Graph (, )][DBLP]

  54. PASAP: power aware structured ASIC placement. [Citation Graph (, )][DBLP]

  55. On stress aware active area sizing, gate sizing, and repeater insertion. [Citation Graph (, )][DBLP]

  56. Skew management of NBTI impacted gated clock trees. [Citation Graph (, )][DBLP]

  57. A high-performance droplet router for digital microfluidic biochips. [Citation Graph (, )][DBLP]

  58. Metal-density driven placement for cmp variation and routability. [Citation Graph (, )][DBLP]

  59. Total sensitivity based dfm optimization of standard library cells. [Citation Graph (, )][DBLP]

  60. Double patterning layout decomposition for simultaneous conflict and stitch minimization. [Citation Graph (, )][DBLP]

  61. Synergistic modeling and optimization for nanometer IC design/manufacturing integration. [Citation Graph (, )][DBLP]

  62. Lithography friendly routing: from construct-by-correction to correct-by-construction. [Citation Graph (, )][DBLP]

  63. OIL: a nano-photonics optical interconnect library for a new photonic networks-on-chip architecture. [Citation Graph (, )][DBLP]

  64. Synthetic Biology Design and Analysis: A Case Study of Frequency Entrained Biological Clock. [Citation Graph (, )][DBLP]

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