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Author:
In-Cheol Park: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Hoon Choi, Hansoo Kim, In-Cheol Park, Seung Ho Hwang, Chong-Min Kyung
    Node Sampling Technique to Speed Up Probability-Based Power Estimation Methods. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:157-160 [Conf]
  2. Young-Su Kwon, In-Cheol Park, Chong-Min Kyung
    A hardware accelerator for the specular intensity of phong illumination model in 3-dimensional graphics. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:559-564 [Conf]
  3. Young-Su Kwon, Bong-Il Park, In-Cheol Park, Chong-Min Kyung
    A New Single-Clock Flip-Clop for Half-Swing Clocking. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:117-120 [Conf]
  4. Woo-Seung Yang, In-Cheol Park, Chong-Min Kyung
    Low-power high-level synthesis using latches. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:462-466 [Conf]
  5. You-Sung Chang, Seungjong Lee, In-Cheol Park, Chong-Min Kyung
    Verification of a Microprocessor Using Real World Applications. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:181-184 [Conf]
  6. Hoon Choi, Ju Hwan Yi, Jong-Yeol Lee, In-Cheol Park, Chong-Min Kyung
    Exploiting Intellectual Properties in ASIP Designs for Embedded DSP Software. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:939-944 [Conf]
  7. Hyeong-Ju Kang, In-Cheol Park
    SAT-based unbounded symbolic model checking. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:840-843 [Conf]
  8. Namseung Kim, Hoon Choi, Seungjong Lee, Seungwang Lee, In-Cheol Park, Chong-Min Kyung
    Virtual Chip: Making Functional Models Work on Real Target Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:170-173 [Conf]
  9. Jong-Yeol Lee, In-Cheol Park
    Timed compiled-code simulation of embedded software for performance analysis of SOC design. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:293-298 [Conf]
  10. In-Cheol Park, Hyeong-Ju Kang
    Digital Filter Synthesis Based on Minimal Signed Digit Representation. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:468-473 [Conf]
  11. In-Cheol Park, Chong-Min Kyung
    Fast and Near Optimal Scheduling in Automatic Data Path Aynthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:680-685 [Conf]
  12. Jin-Hyuk Yang, Byoung-Woon Kim, Sang-Jun Nam, Jang-Ho Cho, Sung-Won Seo, Chang-Ho Ryu, Young-Su Kwon, Dae-Hyun Lee, Jong-Yeol Lee, Jong-Sun Kim, Hyun-Dhong Yoon, Jae-Yeol Kim, Kun-Moo Lee, Chan-Soo Hwang, In-Hyung Kim, Jun Sung Kim, Kwang-Il Park, Kyu Ho Park, Yong-Hoon Lee, Seung Ho Hwang, In-Cheol Park, Chong-Min Kyung
    MetaCore: An Application Specific DSP Development System. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:800-803 [Conf]
  13. Joon-Seo Yim, Yoon-Ho Hwang, Chang-Jae Park, Hoon Choi, Woo-Seung Yang, Hun-Seung Oh, In-Cheol Park, Chong-Min Kyung
    A C-Based RTL Design Verification Methodology for Complex Microprocessor. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:83-88 [Conf]
  14. Ju Hwan Yi, Hoon Choi, In-Cheol Park, Seung Ho Hwang, Chong-Min Kyung
    Multiple Behavior Module Synthesis Based on Selective Groupings. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:384-388 [Conf]
  15. Hoon Choi, Seung Ho Hwang, Chong-Min Kyung, In-Cheol Park
    Synthesis of application specific instructions for embedded DSP software. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:665-671 [Conf]
  16. Se-Kyoung Hong, In-Cheol Park, Chong-Min Kyung
    An O(n3logn)-Heuristic for Microcode Bit Optimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:180-183 [Conf]
  17. Hyeong-Ju Kang, Hansoo Kim, In-Cheol Park
    FIR Filter Synthesis Algorithms for Minimizing the Delay and the Number of Adders. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:51-54 [Conf]
  18. In-Cheol Park, Sehyeon Kang, Yongseok Yi
    Fast Cycle-accurate Behavioral Simulation for Pipelined Processors Using Early Pipeline Evaluation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:138-141 [Conf]
  19. You-Sung Chang, Bong-Il Park, In-Cheol Park, Chong-Min Kyung
    Customization of a CISC Processor Core for Low-Power Applications. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:152-0 [Conf]
  20. Bong-Il Park, Hoon Choi, In-Cheol Park, Chong-Min Kyung
    Synthesis and Optimization of Interface Hardware between IP's Operating at Different Clock Frequencies. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:519-524 [Conf]
  21. Bong-Il Park, In-Cheol Park, Chong-Min Kyung
    A Regular Layout Structured Multiplier Based on Weighted Carry-Save Adders. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:243-0 [Conf]
  22. Myoung-Cheol Shin, Se-Hyeon Kang, In-Cheol Park
    An Area-Efficient Iterative Modified-Booth Multiplier Based on Self-Timed Clocking. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:511-512 [Conf]
  23. Young-Su Kwon, In-Cheol Park, Chong-Min Kyung
    Pyramid Texture Compression and Decompression Using Interpolative Vector Quantization. [Citation Graph (0, 0)][DBLP]
    ICIP, 2000, pp:- [Conf]
  24. Hyung Ki Ahn, In-Cheol Park, Beomsup Kim
    A 5-GHz self-calibrated I/Q clock generator using a quadrature LC-VCO. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:797-800 [Conf]
  25. Hyeong-Ju Kang, In-Cheol Park
    Pairing and ordering to reduce hardware complexity in cascade form filter design. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2003, pp:265-268 [Conf]
  26. Sung-Won Lee, Hyeong-Ju Kang, In-Cheol Park
    A 24-bit floating-point audio DSP controller supporting fast exponentiation. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2003, pp:748-751 [Conf]
  27. Sang-Chul Moon, In-Cheol Park
    Area-efficient memory-based architecture for FFT processing. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:101-104 [Conf]
  28. In-Cheol Park, Se-Hyeon Kang
    Scheduling algorithm for partially parallel architecture of LDPC decoder by matrix permutation. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5778-5781 [Conf]
  29. Seong-Il Park, In-Cheol Park
    History-based memory mode prediction for improving memory performance. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:185-188 [Conf]
  30. Jae Hoon Shim, In-Cheol Park, Beomsup Kim
    A hybrid delta-sigma modulator with adaptive calibration. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:1025-1028 [Conf]
  31. Hyeong-Ju Kang, In-Cheol Park
    Multiplier-less IIR filter synthesis algorithms to trade-off the delay and the number of adders. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:693-696 [Conf]
  32. Jong-Yeol Lee, In-Cheol Park
    Global variable localization and transformation for hardware synthesis from high-level programming language description. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:13-16 [Conf]
  33. Sung-Won Lee, In-Cheol Park
    A low-power variable length decoder based on successive decoding of shoft codewords. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:582-585 [Conf]
  34. Sung-Won Lee, In-Cheol Park
    Quadrature direct digital frequency synthesis using fine-grain angle rotation. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:709-712 [Conf]
  35. Se-Hyeon Kang, In-Cheol Park
    Memory-based low density parity check code decoder architecture using loosely coupled two data-flows. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:397-400 [Conf]
  36. Hyun-Yong Lee, In-Cheol Park
    A fast Reed-Solomon Product-Code decoder without redundant computations. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:381-384 [Conf]
  37. Sung-Won Lee, In-Cheol Park
    Low cost floating-point unit design for audio applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2002, pp:869-872 [Conf]
  38. Myoung-Cheol Shin, Seong-Il Park, Sung-Won Lee, Se-Hyeon Kang, In-Cheol Park
    Area-efficient digital baseband module for Bluetooth wireless communications. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:729-732 [Conf]
  39. Hansoo Kim, In-Cheol Park
    Array address translation for SDRAM-based video processing applications. [Citation Graph (0, 0)][DBLP]
    VCIP, 2000, pp:922-931 [Conf]
  40. Myoung-Cheol Shin, In-Cheol Park
    Optimal down-conversion in compressed DCT domain with minimal operations. [Citation Graph (0, 0)][DBLP]
    VCIP, 2000, pp:1613-1620 [Conf]
  41. Seungjong Lee, Ando Ki, In-Cheol Park, Chong-Min Kyung
    Interface synthesis between software chip model and target board. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2002, v:48, n:1-3, pp:49-57 [Journal]
  42. Hoon Choi, Jong-Sun Kim, Chi-Won Yoon, In-Cheol Park, Seung Ho Hwang, Chong-Min Kyung
    Synthesis of Application Specific Instructions for Embedded DSP Software. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:6, pp:603-614 [Journal]
  43. In-Cheol Park, Se-Kyoung Hong, Chong-Min Kyung
    Two Complementary Approaches for Microcode Bit Optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:2, pp:234-239 [Journal]
  44. Hyeong-Ju Kang, In-Cheol Park
    SAT-based unbounded symbolic model checking. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:2, pp:129-140 [Journal]
  45. Jong-Yeol Lee, In-Cheol Park
    Timed compiled-code functional simulation of embedded software for performance analysis of SOC design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:1, pp:1-14 [Journal]
  46. In-Cheol Park, Hyeong-Ju Kang
    Digital filter synthesis based on an algorithm to generate all minimal signed digit representations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:12, pp:1525-1529 [Journal]
  47. In-Cheol Park, Chong-Min Kyung
    FAMOS: an efficient scheduling algorithm for high-level synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:10, pp:1437-1448 [Journal]
  48. Hansoo Kim, In-Cheol Park
    High-performance and low-power memory-interface architecture for video processing applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2001, v:11, n:11, pp:1160-1170 [Journal]
  49. Jong-Yeol Lee, Seong Ik Cho, In-Cheol Park
    Performance enhancement of embedded software based on new register allocation technique. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2005, v:29, n:4, pp:177-187 [Journal]
  50. Se-Hyeon Kang, In-Cheol Park
    High Speed Sphere Decoding Based on Vertically Incremental Computation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:665-668 [Conf]
  51. Jung-Wook Kim, Jinook Song, SeokHo Lee, In-Cheol Park
    Tiled Interleaving for Multi-Level 2-D Discrete Wavelet Transform. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3984-3987 [Conf]
  52. Ji-Hoon Kim, In-Cheol Park
    Energy-Efficient Double-Binary Tail-Biting Turbo Decoder Based on Border Metric Encoding. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1325-1328 [Conf]
  53. Chung-Hyo Kim, In-Cheol Park
    High speed decoding of context-based adaptive binary arithmetic codes using most probable symbol prediction. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  54. Hye-Mi Choi, Ji-Hoon Kim, In-Cheol Park
    Low-power hybrid turbo decoding based on reverse calculation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  55. Kimo Kim, In-Cheol Park
    Combined image signal processing for CMOS image sensors. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  56. Myoung-Cheol Shin, In-Cheol Park
    SIMD Processor-Based Turbo Decoder Supporting Multiple Third-Generation Wireless Standards. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:7, pp:801-810 [Journal]
  57. Jin-Hyuk Yang, Byoung-Woon Kim, Sang-Joon Nam, Young-Su Kwon, Dae-Hyun Lee, Jong-Yeol Lee, Chan-Soo Hwang, Yong-Hoon Lee, Seung Ho Hwang, In-Cheol Park, Chong-Min Kyung
    MetaCore: an application-specific programmable DSP development system. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:2, pp:173-183 [Journal]

  58. Area and power efficient design of coarse time synchronizer and frequency offset estimator for fixed WiMAX systems. [Citation Graph (, )][DBLP]


  59. Duo-binary circular turbo decoder based on border metric encoding for WiMAX. [Citation Graph (, )][DBLP]


  60. Twiddle factor transformation for pipelined FFT processing. [Citation Graph (, )][DBLP]


  61. Digital filter synthesis considering multiple adder graphs for a coefficient. [Citation Graph (, )][DBLP]


  62. Memory-less bit-plane coder architecture for JPEG2000 with concurrent column-stripe coding. [Citation Graph (, )][DBLP]


  63. Architecture design of a high-performance dual-symbol binary arithmetic coder for JPEG2000. [Citation Graph (, )][DBLP]


  64. Low-power log-MAP turbo decoding based on reduced metric memory access. [Citation Graph (, )][DBLP]


  65. Prediction-based real-time CABAC decoder for high definition H.264/AVC. [Citation Graph (, )][DBLP]


  66. Capacitor array structure and switch control for energy-efficient SAR analog-to-digital converters. [Citation Graph (, )][DBLP]


  67. Fast frequency acquisition all-digital PLL using PVT calibration. [Citation Graph (, )][DBLP]


  68. Small-area and low-energy K-best MIMO detector using relaxed tree expansion and early forwarding. [Citation Graph (, )][DBLP]


  69. Fast and Area-Efficient Sphere Decoding Using Look-Ahead Search. [Citation Graph (, )][DBLP]


  70. Time-Domain Joint Estimation of Fine Symbol Timing Offset and Integer Carrier Frequency Offset. [Citation Graph (, )][DBLP]


  71. Implementation of a High-Throughput and Area-Efficient MIMO Detector Based on Modified Dijkstra's Search. [Citation Graph (, )][DBLP]


  72. Two-Step Aprroach for Coarse Time Synchronization and Frequency Offset Estimation for IEEE 802.16D Systems. [Citation Graph (, )][DBLP]


  73. A novel trace-pipelined binary arithmetic coder architecture for JPEG2000. [Citation Graph (, )][DBLP]


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