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Chong-Min Kyung: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Hoon Choi, Hansoo Kim, In-Cheol Park, Seung Ho Hwang, Chong-Min Kyung
    Node Sampling Technique to Speed Up Probability-Based Power Estimation Methods. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:157-160 [Conf]
  2. Young-Il Kim, Bong-Il Park, Jae-Gon Lee, Chong-Min Kyung
    SmartGlue: an interface controller with auto reconfiguration for field programmable computing machine. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:734-736 [Conf]
  3. Young-Su Kwon, Jae-Gon Lee, Chong-Min Kyung
    Bandwidth tracing arbitration algorithm for mixed-clock SoC with dynamic priority adaptation. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:806-811 [Conf]
  4. Young-Su Kwon, In-Cheol Park, Chong-Min Kyung
    A hardware accelerator for the specular intensity of phong illumination model in 3-dimensional graphics. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:559-564 [Conf]
  5. Young-Su Kwon, Bong-Il Park, In-Cheol Park, Chong-Min Kyung
    A New Single-Clock Flip-Clop for Half-Swing Clocking. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:117-120 [Conf]
  6. Jae-Gon Lee, Wooseung Yang, Young-Su Kwon, Young-Il Kim, Chong-Min Kyung
    Simulation acceleration of transaction-level models for SoC with RTL sub-blocks. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:499-502 [Conf]
  7. Sang-Joon Nam, Jun-Hee Lee, Byoung-Woon Kim, Yeon-Ho Im, Young-Su Kwon, Kyong-Gu Kang, Chong-Min Kyung
    Fast development of source-level debugging system using hardware emulation (short paper). [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:401-404 [Conf]
  8. Jin-Hyuk Yang, Byung-Woon Kim, Sung-Won Seo, Sang-Jun Nam, Chang-Ho Ryu, Jang-Ho Cho, Chong-Min Kyung
    Metacore: A Configurable and Instruction Level Extensible DSP Core. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:325-326 [Conf]
  9. Woo-Seung Yang, In-Cheol Park, Chong-Min Kyung
    Low-power high-level synthesis using latches. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:462-466 [Conf]
  10. You-Sung Chang, Seungjong Lee, In-Cheol Park, Chong-Min Kyung
    Verification of a Microprocessor Using Real World Applications. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:181-184 [Conf]
  11. Hoon Choi, Ju Hwan Yi, Jong-Yeol Lee, In-Cheol Park, Chong-Min Kyung
    Exploiting Intellectual Properties in ASIP Designs for Embedded DSP Software. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:939-944 [Conf]
  12. Namseung Kim, Hoon Choi, Seungjong Lee, Seungwang Lee, In-Cheol Park, Chong-Min Kyung
    Virtual Chip: Making Functional Models Work on Real Target Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:170-173 [Conf]
  13. Young-Il Kim, Woo-Seung Yang, Young-Su Kwon, Chong-Min Kyung
    Communication-efficient hardware acceleration for fast functional simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:293-298 [Conf]
  14. Young-Su Kwon, Young-Il Kim, Chong-Min Kyung
    Systematic functional coverage metric synthesis from hierarchical temporal event relation graph. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:45-48 [Conf]
  15. In-Cheol Park, Chong-Min Kyung
    Fast and Near Optimal Scheduling in Automatic Data Path Aynthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:680-685 [Conf]
  16. Jin-Hyuk Yang, Byoung-Woon Kim, Sang-Jun Nam, Jang-Ho Cho, Sung-Won Seo, Chang-Ho Ryu, Young-Su Kwon, Dae-Hyun Lee, Jong-Yeol Lee, Jong-Sun Kim, Hyun-Dhong Yoon, Jae-Yeol Kim, Kun-Moo Lee, Chan-Soo Hwang, In-Hyung Kim, Jun Sung Kim, Kwang-Il Park, Kyu Ho Park, Yong-Hoon Lee, Seung Ho Hwang, In-Cheol Park, Chong-Min Kyung
    MetaCore: An Application Specific DSP Development System. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:800-803 [Conf]
  17. Joon-Seo Yim, Seong-Ok Bae, Chong-Min Kyung
    A Floorplan-Based Planning Methodology for Power and Clock Distribution in ASICs. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:766-771 [Conf]
  18. Joon-Seo Yim, Yoon-Ho Hwang, Chang-Jae Park, Hoon Choi, Woo-Seung Yang, Hun-Seung Oh, In-Cheol Park, Chong-Min Kyung
    A C-Based RTL Design Verification Methodology for Complex Microprocessor. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:83-88 [Conf]
  19. Joon-Seo Yim, Chong-Min Kyung
    Reducing Cross-Coupling Among Interconnect Wires in Deep-Submicron Datapath Design. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:485-490 [Conf]
  20. Young-Su Kwon, Chong-Min Kyung
    Functional Coverage Metric Generation from Temporal Event Relation Graph. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:670-671 [Conf]
  21. Jae-Gon Lee, Moo-Kyoung Chung, Ki-Yong Ahn, Sang-Heon Lee, Chong-Min Kyung
    A Prediction Packetizing Scheme for Reducing Channel Traffic in Transaction-Level Hardware/Software Co-Emulation. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:384-389 [Conf]
  22. Ju Hwan Yi, Hoon Choi, In-Cheol Park, Seung Ho Hwang, Chong-Min Kyung
    Multiple Behavior Module Synthesis Based on Selective Groupings. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:384-388 [Conf]
  23. Nak-Woong Eum, Taewhan Kim, Chong-Min Kyung
    An accurate evaluation of routing density for symmetrical FPGAs. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:51-55 [Conf]
  24. Kyungsu Kang, Jungsoo Kim, Heejun Shim, Chong-Min Kyung
    Software power estimation using IPI(inter-prefetch interval) power model for advanced off-the-shelf processor. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:594-599 [Conf]
  25. Moo-Kyung Kang, Ju Hwan Yi, You-Sung Chang, Chong-Min Kyung
    Switch Expansion Architecture Using Local Switching Network. [Citation Graph (0, 0)][DBLP]
    ICC (3), 2000, pp:1426-1429 [Conf]
  26. Hoon Choi, Seung Ho Hwang, Chong-Min Kyung, In-Cheol Park
    Synthesis of application specific instructions for embedded DSP software. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:665-671 [Conf]
  27. Sang-Gil Choi, Chong-Min Kyung
    A Floorplanning Algorithm Using Rectangular Voronoi Diagram and Force-Directed Block Shaping. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:56-59 [Conf]
  28. Nak-Woong Eum, Taewhan Kim, Chong-Min Kyung
    A Router for Symmetrical FPGAs Based on Exact Routing Density Evaluation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:137-143 [Conf]
  29. Se-Kyoung Hong, In-Cheol Park, Chong-Min Kyung
    An O(n3logn)-Heuristic for Microcode Bit Optimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:180-183 [Conf]
  30. Young-Il Kim, Chong-Min Kyung
    Automatic translation of behavioral testbench for fully accelerated simulation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:218-221 [Conf]
  31. Chong-Min Kyung, Peter V. Kraus, Dieter A. Mlynski
    Diffusion - An Analytic Procedure Applied to Macro Cell Placement. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:102-105 [Conf]
  32. You-Sung Chang, Bong-Il Park, In-Cheol Park, Chong-Min Kyung
    Customization of a CISC Processor Core for Low-Power Applications. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:152-0 [Conf]
  33. Young-Su Kwon, Bong-Il Park, Chong-Min Kyung
    SCATOMi: Scheduling Driven Circuit Partitioning Algorithm for Multiple FPGAs using Time-multiplexed, Off-chip, Multicasting Interconnection Architecture. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:419-425 [Conf]
  34. Bong-Il Park, Hoon Choi, In-Cheol Park, Chong-Min Kyung
    Synthesis and Optimization of Interface Hardware between IP's Operating at Different Clock Frequencies. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:519-524 [Conf]
  35. Bong-Il Park, In-Cheol Park, Chong-Min Kyung
    A Regular Layout Structured Multiplier Based on Weighted Carry-Save Adders. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:243-0 [Conf]
  36. Young-Su Kwon, In-Cheol Park, Chong-Min Kyung
    Pyramid Texture Compression and Decompression Using Interpolative Vector Quantization. [Citation Graph (0, 0)][DBLP]
    ICIP, 2000, pp:- [Conf]
  37. Byoung-Woon Kim, Chong-Min Kyung
    System-on-Chip design using intellectual properties with imprecise design costs. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:625-628 [Conf]
  38. You-Sung Chang, Bong-Il Park, Chong-Min Kyung
    Conforming inverted data store for low power memory. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1999, pp:91-93 [Conf]
  39. Peter V. Kraus, Dieter A. Mlynski, Chong-Min Kyung
    Diffusion - An analytic procedure applied to global macro cell placment. [Citation Graph (0, 0)][DBLP]
    Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme, 1990, pp:64-74 [Conf]
  40. Moo-Kyoung Chung, Chong-Min Kyung
    Improving Lookahead in Parallel Multiprocessor Simulation Using Dynamic Execution Path Prediction. [Citation Graph (0, 0)][DBLP]
    PADS, 2006, pp:11-18 [Conf]
  41. Moo-Kyoung Chung, Chong-Min Kyung
    Improvement of Compiled Instruction Set Simulator by Increasing Flexibility a. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2004, pp:38-44 [Conf]
  42. Moo-Kyoung Chung, Heejun Shim, Chong-Min Kyung
    Performance Improvement of Multiprocessor Simulation by Optimizing Synchronization a Communication. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:158-164 [Conf]
  43. Young-Su Kwon, Woo-Seung Yang, Chong-Min Kyung
    Signal Scheduling Driven Circuit Partitioning for Multiple FPGAs with Time-multiplexed Interconnection. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:123-128 [Conf]
  44. Chong-Min Kyung, Josef Widder, Dieter A. Mlynski
    Adaptive cluster growth: a new algorithm for circuit placement in rectilinear regions. [Citation Graph (0, 0)][DBLP]
    Computer-Aided Design, 1992, v:24, n:1, pp:27-35 [Journal]
  45. Young-Il Kim, Chong-Min Kyung
    TPartition: Testbench Partitioning for Hardware-Accelerated Functional Verification. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:6, pp:484-493 [Journal]
  46. Ju Hwan Yi, Chong-Min Kyung
    Symbolic Reachability Analysis for Multiple-clock System Design. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2005, v:14, n:3, pp:533-552 [Journal]
  47. Wooseung Yang, Chong-Min Kyung
    Conscep: a Configurable Soc Emulation Platform for C-based Fast Prototyping. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2005, v:14, n:1, pp:137-158 [Journal]
  48. Seungjong Lee, Ando Ki, In-Cheol Park, Chong-Min Kyung
    Interface synthesis between software chip model and target board. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2002, v:48, n:1-3, pp:49-57 [Journal]
  49. Moo-Kyoung Chung, Chong-Min Kyung
    Enhancing Performance of HW/SW Cosimulation and Coemulation by Reducing Communication Overhead. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:2, pp:125-136 [Journal]
  50. Hoon Choi, Jong-Sun Kim, Chi-Won Yoon, In-Cheol Park, Seung Ho Hwang, Chong-Min Kyung
    Synthesis of Application Specific Instructions for Embedded DSP Software. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:6, pp:603-614 [Journal]
  51. Nak-Woong Eum, Taewhan Kim, Chong-Min Kyung
    CeRA: A Router for Symmetrical FPGAs Based on Exact Routing Density Evaluation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:7, pp:829-842 [Journal]
  52. In-Cheol Park, Se-Kyoung Hong, Chong-Min Kyung
    Two Complementary Approaches for Microcode Bit Optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:2, pp:234-239 [Journal]
  53. Sung-Soo Kim, Chong-Min Kyung
    Circuit placement on arbitrarily shaped regions using the self-organization principle. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:7, pp:844-854 [Journal]
  54. Young-Su Kwon, Chong-Min Kyung
    Performance-driven event-based synchronization for multi-FPGA simulation accelerator with event time-multiplexing bus. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:9, pp:1444-1456 [Journal]
  55. In-Cheol Park, Chong-Min Kyung
    FAMOS: an efficient scheduling algorithm for high-level synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:10, pp:1437-1448 [Journal]
  56. Yeong-Yil Yang, Chong-Min Kyung
    HALO: an efficient global placement strategy for standard cells. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:8, pp:1024-1031 [Journal]
  57. Hyun-Joon Kim, Chong-Min Kyung
    A new parallel ray-tracing system based on object decomposition. [Citation Graph (0, 0)][DBLP]
    The Visual Computer, 1996, v:12, n:5, pp:244-253 [Journal]
  58. Young-Su Kwon, Chong-Min Kyung
    Scheduling driven circuit partitioning algorithm for multiple FPGAs using time-multiplexed, off-chip, multi-casting interconnection architecture. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2004, v:28, n:5-6, pp:341-350 [Journal]
  59. Woong Hwangbo, Jaemoon Kim, Chong-Min Kyung
    A High-Performance 2-D Inverse Transform Architecture for the H.264/AVC Decoder. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1613-1616 [Conf]
  60. Sung-Joon Jang, Moo-Kyoung Chung, Jaemoon Kim, Chong-Min Kyung
    Cache Miss-Aware Dynamic Stack Allocation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3494-3497 [Conf]
  61. Jae-Gon Lee, Moo-Kyoung Chung, Ki-Yong Ahn, Sang-Heon Lee, Chong-Min Kyung
    A Prediction Packetizing Scheme for Reducing Channel Traffic in Transaction-Level Hardware/Software Co-Emulation [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  62. Jin-Hyuk Yang, Byoung-Woon Kim, Sang-Joon Nam, Young-Su Kwon, Dae-Hyun Lee, Jong-Yeol Lee, Chan-Soo Hwang, Yong-Hoon Lee, Seung Ho Hwang, In-Cheol Park, Chong-Min Kyung
    MetaCore: an application-specific programmable DSP development system. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:2, pp:173-183 [Journal]
  63. Byoung-Woon Kim, Chong-Min Kyung
    Exploiting intellectual properties with imprecise design costs for system-on-chip synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:3, pp:240-252 [Journal]
  64. You-Sung Chang, Chong-Min Kyung
    Conforming block inversion for low power memory. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:1, pp:15-19 [Journal]

  65. Program phase and runtime distribution-aware online DVFS for combined Vdd/Vbb scaling. [Citation Graph (, )][DBLP]


  66. Adaptive Cluster Growth (ACG): a new algorithm for circuit packing in rectilinear region. [Citation Graph (, )][DBLP]


  67. Search Area Selective Reuse Algorithm in Motion Estimation. [Citation Graph (, )][DBLP]


  68. A lossless embedded compression algorithm for high definition video coding. [Citation Graph (, )][DBLP]


  69. A Multi-layer motion estimation scheme for spatial scalability in H.264/AVC scalable extension. [Citation Graph (, )][DBLP]


  70. A low cost single-pass fractional motion estimation architecture using bit clipping for H.264 video codec. [Citation Graph (, )][DBLP]


  71. Event statistics and criticality-aware bitrate allocation to minimize energy consumption of memory-constrained wireless surveillance system. [Citation Graph (, )][DBLP]


  72. Low latency variable length coding scheme for frame memory recompression. [Citation Graph (, )][DBLP]


  73. Data Reuse method between Heterogeneous Partitions (DRHP) in H.264/AVC motion compensator. [Citation Graph (, )][DBLP]


  74. Task partitioning algorithm for intra-task dynamic voltage scaling. [Citation Graph (, )][DBLP]


  75. Energy-aware instruction-set customization for real-time embedded multiprocessor systems. [Citation Graph (, )][DBLP]


  76. A low-power deblocking filter architecture for H.264 advanced video coding. [Citation Graph (, )][DBLP]


  77. Fast estimation of software energy consumption using IPI(Inter-Prefetch Interval) energy model. [Citation Graph (, )][DBLP]


  78. An early block type decision method for intra prediction in H.264/AVC. [Citation Graph (, )][DBLP]


  79. A fast CABAC rate estimator for H.264/AVC mode decision. [Citation Graph (, )][DBLP]


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