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Nozomu Togawa: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jinku Choi, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa
    VLSI Architecture for a Flexible Motion Estimation with Parameters. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:452-457 [Conf]
  2. Shunitsu Kohara, Naoki Tomono, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
    An interface-circuit synthesis method with configurable processor core in IP-based SoC designs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:594-599 [Conf]
  3. Yuichiro Miyaoka, Yoshiharu Kataoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
    Area/delay estimation for digital signal processor cores. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:156-161 [Conf]
  4. Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
    A cosynthesis algorithm for application specific processors with heterogeneous datapaths. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:250-255 [Conf]
  5. Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki
    FCSCAN: an efficient multiscan-based test compression technique for test cost reduction. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:653-658 [Conf]
  6. Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto
    Reconfigurable adaptive FEC system with interleaving. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1252-1255 [Conf]
  7. Nozomu Togawa, Takafumi Hisaki, Masao Yanagisawa, Tatsuo Ohtsuki
    A High-Level Synthesis System for Digital Signal Processing Based on Enumerating Data-Flow Graphs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:265-274 [Conf]
  8. Nozomu Togawa, Kayoko Hagi, Masao Yanagisawa, Tatsuo Ohtsuki
    An Incremental Placement and Global Routing Algorithm for Field-Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:519-526 [Conf]
  9. Nozomu Togawa, Masayuki Ienaga, Masao Yanagisawa, Tatsuo Ohtsuki
    An area/time optimizing algorithm in high-level synthesis for control-based hardwares (short paper). [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:309-312 [Conf]
  10. Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki
    Maple-opt: a simultaneous technology mapping, placement, and global routing algorithm FPGAs with performance optimization. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  11. Nozomu Togawa, Takashi Sakurai, Masao Yanagisawa, Tatsuo Ohtsuki
    A Hardware/Software Partitioning Algorithm for Processor Cores of Digital Signal Processing. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:335-338 [Conf]
  12. Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki
    Instruction set and functional unit synthesis for SIMD processor cores. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:743-750 [Conf]
  13. Naoki Tomono, Shunitsu Kohara, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
    A processor core synthesis system in IP-based SoC design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:286-291 [Conf]
  14. Jumpei Uchida, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
    A thread partitioning algorithm in low power high-level synthesis. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:74-79 [Conf]
  15. Youhua Shi, Shinji Kimura, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
    Alternative Run-Length Coding through Scan Chain Reconfiguration for Joint Minimization of Test Data Volume and Power Consumption in Scan Test. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:432-437 [Conf]
  16. Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, Shinji Kimura
    Low Power Test Compression Technique for Designs with Multiple Scan Chain. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:386-389 [Conf]
  17. Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki
    A simultaneous technology mapping, placement, and global routing algorithm for field-programmable gate arrays. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:156-163 [Conf]
  18. Kazunori Shimizu, Tatsuyuki Ishikawa, Takeshi Ikenaga, Satoshi Goto, Nozomu Togawa
    Partially-Parallel LDPC Decoder Based on High-Efficiency Message-Passing Algorithm. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:503-510 [Conf]
  19. Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki
    A Simultaneous Placement and Global Routing Algorithm for FPGAs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:483-486 [Conf]
  20. Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
    VLSI Architecture for a Flexible Motion Estimation with Parameters. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:452-457 [Conf]
  21. Nozomu Togawa, Kaoru Ukai, Masao Yanagisawa, Tatsuo Ohtsuki
    A Simultaneous Placement and Global Routing Algorithm for FPGAs with Power Optimization. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 1999, v:9, n:1-2, pp:9-112 [Journal]
  22. Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
    Maple-opt: a performance-oriented simultaneous technology mapping, placement, and global routing algorithm for FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:9, pp:803-818 [Journal]
  23. Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
    Design for Secure Test - A Case Study on Pipelined Advanced Encryption Standard. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:149-152 [Conf]
  24. Kazunori Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto
    A parallel LSI architecture for LDPC decoder improving message-passing schedule. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]

  25. Exact and fast L1 cache simulation for embedded systems. [Citation Graph (, )][DBLP]


  26. Scalable unified dual-radix architecture for Montgomery multiplication in GF(P) and GF(2n). [Citation Graph (, )][DBLP]


  27. GECOM: Test data compression combined with all unknown response masking. [Citation Graph (, )][DBLP]


  28. Sub-operation parallelism optimization in SIMD processor synthesis and its experimental evaluations. [Citation Graph (, )][DBLP]


  29. Power-efficient LDPC code decoder architecture. [Citation Graph (, )][DBLP]


  30. Memory-Efficient Accelerating Schedule for LDPC Decoder. [Citation Graph (, )][DBLP]


  31. An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions. [Citation Graph (, )][DBLP]


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