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Yih-Chih Chou: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yih-Chih Chou, Youn-Long Lin
    A 3-step approach for performance-driven whole-chip routing. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:187-191 [Conf]
  2. Yih-Chih Chou, Youn-Long Lin
    A graph-partitioning-based approach for multi-layer constrained via minimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:426-429 [Conf]
  3. Tzu-Chieh Tien, Hsiao-Pin Su, Yu-Wen Tsay, Yih-Chih Chou, Youn-Long Lin
    Integrating logic retiming and register placement. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:136-139 [Conf]
  4. Yih-Chih Chou, Youn-Long Lin
    A performance-driven standard-cell placer based on a modified force-directed algorithm. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:24-29 [Conf]
  5. Yih-Chih Chou, Youn-Long Lin
    Effective enforcement of path-delay constraints inperformance-driven placement. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:1, pp:15-22 [Journal]

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