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Charlie Chung-Ping Chen: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Hsinwei Chou, Yu-Hao Wang, Charlie Chung-Ping Chen
    Fast and effective gate-sizing with multiple-Vt assignment using generalized Lagrangian Relaxation. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:381-386 [Conf]
  2. Rong Jiang, Charlie Chung-Ping Chen
    Comprehensive frequency dependent interconnect extraction and evaluation methodology. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1070-1073 [Conf]
  3. Yu-Min Lee, Hing Yin Lai, Charlie Chung-Ping Chen
    Optimal spacing and capacitance padding for general clock structures. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:115-119 [Conf]
  4. Clement Luk, Tsung-Hao Chen, Charlie Chung-Ping Chen
    Frequency-dependent reluctance extraction. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:792-797 [Conf]
  5. Jeng-Liang Tsai, Charlie Chung-Ping Chen
    Process-variation robust and low-power zero-skew buffered clock-tree synthesis using projected scan-line sampling. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1168-1171 [Conf]
  6. Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen
    Wave-pipelined on-chip global interconnect. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:127-132 [Conf]
  7. Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen
    Block based statistical timing analysis with extended canonical timing model. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:250-253 [Conf]
  8. Lizheng Zhang, Jeng-Liang Tsai, Weijen Chen, Yuhen Hu, Charlie Chung-Ping Chen
    Convergence-provable statistical timing analysis with level-sensitive latches and feedback loops. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:941-946 [Conf]
  9. Yahong Cao, Yu-Min Lee, Tsung-Hao Chen, Charlie Chung-Ping Chen
    HiPRIME: hierarchical and passivity reserved interconnect macromodeling engine for RLKC power delivery. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:379-384 [Conf]
  10. Tsung-Hao Chen, Charlie Chung-Ping Chen
    Efficient Large-Scale Power Grid Analysis Based on Preconditioned Krylov-Subspace Iterative Methods. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:559-562 [Conf]
  11. Rong Jiang, Yi-Hao Chang, Charlie Chung-Ping Chen
    ICCAP: a linear time sparse transformation and reordering algorithm for 3D BEM capacitance extraction. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:163-166 [Conf]
  12. Lizheng Zhang, Weijen Chen, Yuhen Hu, John A. Gubner, Charlie Chung-Ping Chen
    Correlation-preserved non-gaussian statistical timing analysis with quadratic timing model. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:83-88 [Conf]
  13. Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen
    Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:904-907 [Conf]
  14. Rong Jiang, Charlie Chung-Ping Chen
    SCORE: SPICE COmpatible Reluctance Extraction. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:948-953 [Conf]
  15. Rong Jiang, Charlie Chung-Ping Chen
    Realizable Reduction for Electromagnetically Coupled RLMC Interconnects. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1400-1401 [Conf]
  16. Yu-Min Lee, Charlie Chung-Ping Chen
    The Power Grid Transient Simulation in Linear Time Based on 3D Alternating-Direction-Implicit Method . [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11020-11025 [Conf]
  17. Ting-Yuan Wang, Jeng-Liang Tsai, Charlie Chung-Ping Chen
    Thermal and Power Integrity Based Power/Ground Networks Optimization. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:830-835 [Conf]
  18. Lizheng Zhang, Weijen Chen, Yuhen Hu, Charlie Chung-Ping Chen
    Statistical Timing Analysis with Extended Pseudo-Canonical Timing Model. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:952-957 [Conf]
  19. Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen
    Statistical timing analysis with path reconvergence and spatial correlations. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:528-532 [Conf]
  20. Yu-Min Lee, Charlie Chung-Ping Chen
    Hierarchical model order reduction for signal-integrity interconnect synthesis. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:109-114 [Conf]
  21. Tsung-Hao Chen, Clement Luk, Charlie Chung-Ping Chen
    SuPREME: Substrate and Power-delivery Reluctance-Enhanced Macromodel Evaluation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:786-792 [Conf]
  22. Tsung-Hao Chen, Clement Luk, Hyungsuk Kim, Charlie Chung-Ping Chen
    INDUCTWISE: inductance-wise interconnect simulator and extractor. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:215-220 [Conf]
  23. Charlie Chung-Ping Chen, Tae-Woo Lee, Narayanan Murugesan, Susan C. Hagness
    Generalized FDTD-ADI: An Unconditionally Stable Full-Wave Maxwell's Equations Solver for VLSI Interconnect Modeling. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:156-163 [Conf]
  24. Rong Jiang, Wenyin Fu, Janet Meiling Wang, Vince Lin, Charlie Chung-Ping Chen
    Efficient statistical capacitance variability modeling with orthogonal principle factor analysis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:683-690 [Conf]
  25. Yu-Min Lee, Charlie Chung-Ping Chen
    Power Grid Transient Simulation in Linear Time Based on Transmission-Line-Modeling Alternating-Direction-Implicit Method. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:75-0 [Conf]
  26. Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja
    A yield improvement methodology using pre- and post-silicon statistical clock scheduling. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:611-618 [Conf]
  27. Janet Meiling Wang, Bharat Srinivas, Dongsheng Ma, Charlie Chung-Ping Chen, Jun Li
    System-level power and thermal modeling and analysis by orthogonal polynomial based response surface approach (OPRS). [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:728-735 [Conf]
  28. Saisanthosh Balakrishnan, Jong Hyuk Park, Hyungsuk Kim, Yu-Min Lee, Charlie Chung-Ping Chen
    Linear Time Hierarchical Capacitance Extraction without Multipole Expansion. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:98-103 [Conf]
  29. Pradeepsunder Ganesh, Charlie Chung-Ping Chen
    RC-in RC-out Model Order Reduction Accurate up to Second Order Moments. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:505-506 [Conf]
  30. Rong Jiang, Tsung-Hao Chen, Charlie Chung-Ping Chen
    PODEA: Power delivery efficient analysis with realizable model reduction. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2003, pp:608-611 [Conf]
  31. Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Ping Chen
    Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time. [Citation Graph (0, 0)][DBLP]
    ISPD, 2003, pp:166-173 [Conf]
  32. Ting-Yuan Wang, Charlie Chung-Ping Chen
    Thermal-ADI: a linear-time chip-level dynamic thermal simulation algorithm based on alternating-direction-implicit (ADI) method. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:238-243 [Conf]
  33. Ting-Yuan Wang, Yu-Min Lee, Charlie Chung-Ping Chen
    3D thermal-ADI: an efficient chip-level transient thermal simulator. [Citation Graph (0, 0)][DBLP]
    ISPD, 2003, pp:10-17 [Conf]
  34. Ting-Yuan Wang, Jeng-Liang Tsai, Charlie Chung-Ping Chen
    Sensitivity guided net weighting for placement driven synthesis. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:124-131 [Conf]
  35. Lizheng Zhang, Jun Shao, Charlie Chung-Ping Chen
    Non-gaussian statistical parameter modeling for SSTA with confidence interval analysis. [Citation Graph (0, 0)][DBLP]
    ISPD, 2006, pp:33-38 [Conf]
  36. Charlie Chung-Ping Chen, Ed Cheng
    Future SoC Design Challenges and Solutions (invited). [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:534-538 [Conf]
  37. Sanghamitra Roy, Charlie Chung-Ping Chen
    ConvexSmooth: A simultaneous convex fitting and smoothing algorithm for convex optimization problems. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:665-670 [Conf]
  38. Ting-Yuan Wang, Charlie Chung-Ping Chen
    Optimization of the Power/Ground Network Wire-Sizing and Spacing Based on Sequential Network Simplex Algorithm. [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:157-162 [Conf]
  39. Ting-Yuan Wang, Charlie Chung-Ping Chen
    SPICE-Compatible Thermal Simulation with Lumped Circuit Modeling for Thermal Reliability Analysis Based on Modeling Order Reduction. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:357-362 [Conf]
  40. Dongkeun Oh, Charlie Chung Ping Chen, Yu Hen Hu
    3DFFT: Thermal Analysis of Non-Homogeneous IC Using 3D FFT Green Function Method. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:567-572 [Conf]
  41. Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja
    False Path and Clock Scheduling Based Yield-Aware Gate Sizing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:423-426 [Conf]
  42. Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja
    Yield-Driven, False-Path-Aware Clock Skew Scheduling. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:3, pp:214-222 [Journal]
  43. Tsung-Hao Chen, Clement Luk, Charlie Chung-Ping Chen
    INDUCTWISE: inductance-wise interconnect simulator and extractor. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:7, pp:884-894 [Journal]
  44. Rong Jiang, Wenyin Fu, Charlie Chung-Ping Chen
    EPEEC: comprehensive SPICE-compatible reluctance extraction for high-speed interconnects above lossy multilayer substrates. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:10, pp:1562-1571 [Journal]
  45. Yu-Min Lee, Charlie Chung-Ping Chen
    Power grid transient simulation in linear time based on transmission-line-modeling alternating-direction-implicit method. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:11, pp:1343-1352 [Journal]
  46. Yu-Min Lee, Charlie Chung-Ping Chen
    The power grid transient simulation in linear time based on 3-D alternating-direction-implicit method. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:11, pp:1545-1550 [Journal]
  47. Yu-Min Lee, Yahong Cao, Tsung-Hao Chen, Janet Meiling Wang, Charlie Chung-Ping Chen
    HiPRIME: hierarchical and passivity preserved interconnect macromodeling engine for RLKC power delivery. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:6, pp:797-806 [Journal]
  48. Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Ping Chen
    Zero skew clock-tree optimization with buffer insertion/sizing and wire sizing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:4, pp:565-572 [Journal]
  49. Ting-Yuan Wang, Charlie Chung-Ping Chen
    3-D Thermal-ADI: a linear-time chip level transient thermal simulator. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:12, pp:1434-1445 [Journal]
  50. Lizheng Zhang, Weijen Chen, Yuhen Hu, John A. Gubner, Charlie Chung-Ping Chen
    Correlation-Preserved Statistical Timing With a Quadratic Form of Gaussian Variables. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2437-2449 [Journal]
  51. Lizheng Zhang, Weijen Chen, Yuhen Hu, Charlie Chung-Ping Chen
    Statistical static timing analysis with conditional linear MAX/MIN approximation and extended canonical timing model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:1183-1191 [Journal]
  52. Pei-Yu Huang, Yu-Min Lee, Jeng-Liang Tsai, Charlie Chung-Ping Chen
    Simultaneous area minimization and decaps insertion for power delivery network using adjoint sensitivity analysis with IEKS method. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  53. Ting-Yuan Wang, Charlie Chung-Ping Chen
    Thermal-ADI - a linear-time chip-level dynamic thermal-simulation algorithm based on alternating-direction-implicit (ADI) method. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:4, pp:691-700 [Journal]

  54. SmartSmooth: A linear time convexity preserving smoothing algorithm for numerically convex data with application to VLSI design. [Citation Graph (, )][DBLP]


  55. An optimal algorithm for sizing sequential circuits for industrial library based designs. [Citation Graph (, )][DBLP]


  56. LTCC spiral inductor modeling, synthesis, and optimization. [Citation Graph (, )][DBLP]


  57. Accurate and analytical statistical spatial correlation modeling for VLSI DFM applications. [Citation Graph (, )][DBLP]


  58. Process-Variation Statistical Modeling for VLSI Timing Analysis. [Citation Graph (, )][DBLP]


  59. The compatibility analysis of thread migration and DVFS in multi-core processor. [Citation Graph (, )][DBLP]


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