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Zhiru Zhang: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jason Cong, Yiping Fan, Guoling Han, Yizhou Lin, Junjuan Xu, Zhiru Zhang, Xu Cheng
    Bitwidth-aware scheduling and binding in high-level synthesis. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:856-861 [Conf]
  2. Jason Cong, Yiping Fan, Guoling Han, Xun Yang, Zhiru Zhang
    Architecture and synthesis for multi-cycle on-chip communication. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2003, pp:77-78 [Conf]
  3. Jason Cong, Yiping Fan, Guoling Han, Wei Jiang, Zhiru Zhang
    Behavior and communication co-optimization for systems with sequential communication media. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:675-678 [Conf]
  4. Jason Cong, Yiping Fan, Zhiru Zhang
    Architecture-level synthesis for automatic interconnect pipelining. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:602-607 [Conf]
  5. Jason Cong, Zhiru Zhang
    An efficient and versatile scheduling algorithm based on SDC formulation. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:433-438 [Conf]
  6. Jason Cong, Yiping Fan, Guoling Han, Ashok Jagannathan, Glenn Reinman, Zhiru Zhang
    Instruction set extension with shadow registers for configurable processors. [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:99-106 [Conf]
  7. Jason Cong, Yiping Fan, Guoling Han, Zhiru Zhang
    Application-specific instruction generation for configurable processor architectures. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:183-189 [Conf]
  8. Jason Cong, Yiping Fan, Guoling Han, Xun Yang, Zhiru Zhang
    Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:536-543 [Conf]
  9. Jason Cong, Guoling Han, Zhiru Zhang
    Architecture and compilation for data bandwidth improvement in configurable embedded processors. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:263-270 [Conf]
  10. Zhiru Zhang, Yiping Fan, Miodrag Potkonjak, Jason Cong
    Gradual Relaxation Techniques with Applications to Behavioral Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:529-535 [Conf]
  11. Jason Cong, Yiping Fan, Xun Yang, Zhiru Zhang
    Architecture and synthesis for multi-cycle communication. [Citation Graph (0, 0)][DBLP]
    ISPD, 2003, pp:190-196 [Conf]
  12. Jason Cong, Yiping Fan, Guoling Han, Xun Yang, Zhiru Zhang
    Architecture and synthesis for on-chip multicycle communication. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:4, pp:550-564 [Journal]
  13. Jason Cong, Guoling Han, Zhiru Zhang
    Architecture and Compiler Optimizations for Data Bandwidth Improvement in Configurable Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:9, pp:986-997 [Journal]

  14. Scheduling with integer time budgeting for low-power optimization. [Citation Graph (, )][DBLP]


  15. Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA. [Citation Graph (, )][DBLP]


  16. High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs. [Citation Graph (, )][DBLP]


  17. Evaluation of Static Analysis Techniques for Fixed-Point Precision Optimization. [Citation Graph (, )][DBLP]


  18. Revisiting bitwidth optimizations. [Citation Graph (, )][DBLP]


  19. Bit-level optimization for high-level synthesis and FPGA-based acceleration. [Citation Graph (, )][DBLP]


  20. Scheduling with soft constraints. [Citation Graph (, )][DBLP]


  21. Behavior-level observability don't-cares and application to low-power behavioral synthesis. [Citation Graph (, )][DBLP]


  22. Image classification with spectral and texture features based on SVM. [Citation Graph (, )][DBLP]


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