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Ashok Jagannathan: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jason Cong, Ashok Jagannathan, Yuchun Ma, Glenn Reinman, Jie Wei, Yan Zhang
    An automated design flow for 3D microarchitecture evaluation. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:384-389 [Conf]
  2. Ashok Jagannathan, Hannah Honghua Yang, Kris Konigsfeld, Dan Milliron, Mosur Mohan, Michail Romesis, Glenn Reinman, Jason Cong
    Microarchitecture evaluation with floorplanning and interconnect pipelining. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:8-15 [Conf]
  3. Jason Cong, Ashok Jagannathan, Glenn Reinman, Michail Romesis
    Microarchitecture evaluation with physical planning. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:32-35 [Conf]
  4. Ashok Jagannathan, Sung-Woo Hur, John Lillis
    A fast algorithm for context-aware buffer insertion. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:368-373 [Conf]
  5. Jason Cong, Yiping Fan, Guoling Han, Ashok Jagannathan, Glenn Reinman, Zhiru Zhang
    Instruction set extension with shadow registers for configurable processors. [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:99-106 [Conf]
  6. Jason Cong, Ashok Jagannathan, Glenn Reinman, Yuval Tamir
    Understanding the energy efficiency of SMT and CMP with multiclustering. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:48-53 [Conf]
  7. Sung-Woo Hur, Ashok Jagannathan, John Lillis
    Timing driven maze routing. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:208-213 [Conf]
  8. Sung-Woo Hur, Ashok Jagannathan, John Lillis
    Timing-driven maze routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:2, pp:234-241 [Journal]
  9. Ashok Jagannathan, Sung-Woo Hur, John Lillis
    A fast algorithm for context-aware buffer insertion. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:1, pp:173-188 [Journal]
  10. Jason Cong, Guoling Han, Ashok Jagannathan, Glenn Reinman, Krzysztof Rutkowski
    Accelerating Sequential Applications on CMPs Using Core Spilling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2007, v:18, n:8, pp:1094-1107 [Journal]

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