Search the dblp DataBase
Ashok Jagannathan: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]
Publications of Author
- Jason Cong, Ashok Jagannathan, Yuchun Ma, Glenn Reinman, Jie Wei, Yan Zhang
An automated design flow for 3D microarchitecture evaluation. [Citation Graph (0, 0)][DBLP]
ASP-DAC, 2006, pp:384-389 [Conf] - Ashok Jagannathan, Hannah Honghua Yang, Kris Konigsfeld, Dan Milliron, Mosur Mohan, Michail Romesis, Glenn Reinman, Jason Cong
Microarchitecture evaluation with floorplanning and interconnect pipelining. [Citation Graph (0, 0)][DBLP]
ASP-DAC, 2005, pp:8-15 [Conf] - Jason Cong, Ashok Jagannathan, Glenn Reinman, Michail Romesis
Microarchitecture evaluation with physical planning. [Citation Graph (0, 0)][DBLP]
DAC, 2003, pp:32-35 [Conf] - Ashok Jagannathan, Sung-Woo Hur, John Lillis
A fast algorithm for context-aware buffer insertion. [Citation Graph (0, 0)][DBLP]
DAC, 2000, pp:368-373 [Conf] - Jason Cong, Yiping Fan, Guoling Han, Ashok Jagannathan, Glenn Reinman, Zhiru Zhang
Instruction set extension with shadow registers for configurable processors. [Citation Graph (0, 0)][DBLP]
FPGA, 2005, pp:99-106 [Conf] - Jason Cong, Ashok Jagannathan, Glenn Reinman, Yuval Tamir
Understanding the energy efficiency of SMT and CMP with multiclustering. [Citation Graph (0, 0)][DBLP]
ISLPED, 2005, pp:48-53 [Conf] - Sung-Woo Hur, Ashok Jagannathan, John Lillis
Timing driven maze routing. [Citation Graph (0, 0)][DBLP]
ISPD, 1999, pp:208-213 [Conf] - Sung-Woo Hur, Ashok Jagannathan, John Lillis
Timing-driven maze routing. [Citation Graph (0, 0)][DBLP]
IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:2, pp:234-241 [Journal] - Ashok Jagannathan, Sung-Woo Hur, John Lillis
A fast algorithm for context-aware buffer insertion. [Citation Graph (0, 0)][DBLP]
ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:1, pp:173-188 [Journal] - Jason Cong, Guoling Han, Ashok Jagannathan, Glenn Reinman, Krzysztof Rutkowski
Accelerating Sequential Applications on CMPs Using Core Spilling. [Citation Graph (0, 0)][DBLP]
IEEE Trans. Parallel Distrib. Syst., 2007, v:18, n:8, pp:1094-1107 [Journal]
Search in 0.002secs, Finished in 0.002secs
| NOTICE1 |
|---|
| System may not be available sometimes or not working properly, since it is still in development with continuous upgrades |
| NOTICE2 |
|---|
| The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP |
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002