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Glenn Reinman: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jason Cong, Ashok Jagannathan, Yuchun Ma, Glenn Reinman, Jie Wei, Yan Zhang
    An automated design flow for 3D microarchitecture evaluation. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:384-389 [Conf]
  2. Ashok Jagannathan, Hannah Honghua Yang, Kris Konigsfeld, Dan Milliron, Mosur Mohan, Michail Romesis, Glenn Reinman, Jason Cong
    Microarchitecture evaluation with floorplanning and interconnect pipelining. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:8-15 [Conf]
  3. Thomas Y. Yeh, Glenn Reinman
    Fast and fair: data-stream quality of service. [Citation Graph (0, 0)][DBLP]
    CASES, 2005, pp:237-248 [Conf]
  4. Anahita Shayesteh, Glenn Reinman, Norman P. Jouppi, Timothy Sherwood, Suleyman Sair
    Improving the performance and power efficiency of shared helpers in CMPs. [Citation Graph (0, 0)][DBLP]
    CASES, 2006, pp:345-356 [Conf]
  5. Jason Cong, Ashok Jagannathan, Glenn Reinman, Michail Romesis
    Microarchitecture evaluation with physical planning. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:32-35 [Conf]
  6. Jason Cong, Yiping Fan, Guoling Han, Ashok Jagannathan, Glenn Reinman, Zhiru Zhang
    Instruction set extension with shadow registers for configurable processors. [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:99-106 [Conf]
  7. Gokhan Memik, Glenn Reinman, William H. Mangione-Smith
    Just Say No: Benefits of Early Cache Miss Determinatio. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:307-316 [Conf]
  8. Yongxiang Liu, Gokhan Memik, Glenn Reinman
    Reducing the Energy of Speculative Instruction Schedulers. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:641-646 [Conf]
  9. Anahita Shayesteh, Eren Kursun, Timothy Sherwood, Suleyman Sair, Glenn Reinman
    Reducing the Latency and Area Cost of Core Swapping through Shared Helper Engines. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:17-23 [Conf]
  10. Yongxiang Liu, Anahita Shayesteh, Gokhan Memik, Glenn Reinman
    Scaling the issue window with look-ahead latency prediction. [Citation Graph (0, 0)][DBLP]
    ICS, 2004, pp:217-226 [Conf]
  11. Yongxiang Liu, Anahita Shayesteh, Gokhan Memik, Glenn Reinman
    Tornado warning: the perils of selective replay in multithreaded processors. [Citation Graph (0, 0)][DBLP]
    ICS, 2005, pp:51-60 [Conf]
  12. Glenn Reinman, Brad Calder, Dean M. Tullsen, Gary S. Tyson, Todd M. Austin
    Classifying load and store instructions for memory renaming. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1999, pp:399-407 [Conf]
  13. Brad Calder, Glenn Reinman, Dean M. Tullsen
    Selective Value Prediction. [Citation Graph (0, 0)][DBLP]
    ISCA, 1999, pp:64-74 [Conf]
  14. Glenn Reinman, Todd M. Austin, Brad Calder
    A Scalable Front-End Architecture for Fast Instruction Delivery. [Citation Graph (0, 0)][DBLP]
    ISCA, 1999, pp:234-245 [Conf]
  15. Glenn Reinman, Brad Calder, Todd M. Austin
    High Performance and Energy Efficient Serial Prefetch Architecture. [Citation Graph (0, 0)][DBLP]
    ISHPC, 2002, pp:146-159 [Conf]
  16. Jason Cong, Ashok Jagannathan, Glenn Reinman, Yuval Tamir
    Understanding the energy efficiency of SMT and CMP with multiclustering. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:48-53 [Conf]
  17. Gokhan Memik, Glenn Reinman, William H. Mangione-Smith
    Reducing energy and delay using efficient victim caches. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:262-265 [Conf]
  18. Glenn Reinman, Brad Calder
    Predictive Techniques for Aggressive Load Speculation. [Citation Graph (0, 0)][DBLP]
    MICRO, 1998, pp:127-137 [Conf]
  19. Glenn Reinman, Brad Calder, Todd M. Austin
    Fetch Directed Instruction Prefetching. [Citation Graph (0, 0)][DBLP]
    MICRO, 1999, pp:16-27 [Conf]
  20. Eren Kursun, Glenn Reinman, Suleyman Sair, Anahita Shayesteh, Timothy Sherwood
    Low-Overhead Core Swapping for Thermal Management. [Citation Graph (0, 0)][DBLP]
    PACS, 2004, pp:46-60 [Conf]
  21. Vasily G. Moshnyaga, Hoa Vo, Glenn Reinman, Miodrag Potkonjak
    Handheld System Energy Reduction by OS-Driven Refresh. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2006, pp:24-35 [Conf]
  22. Brad Calder, Glenn Reinman
    A Comparative Survey of Load Speculation Architectures. [Citation Graph (0, 0)][DBLP]
    J. Instruction-Level Parallelism, 2000, v:2, n:, pp:- [Journal]
  23. Glenn Reinman, Brad Calder
    Using a serial cache for energy efficient instruction fetching. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2004, v:50, n:11, pp:675-685 [Journal]
  24. Anahita Shayesteh, Glenn Reinman, Norman P. Jouppi, Suleyman Sair, Timothy Sherwood
    Dynamically configurable shared CMP helper engines for improved performance. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2005, v:33, n:4, pp:70-79 [Journal]
  25. Glenn Reinman, Brad Calder, Todd M. Austin
    Optimizations Enabled by a Decoupled Front-End Architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:4, pp:338-355 [Journal]
  26. Thomas Y. Yeh, Petros Faloutsos, Sanjay J. Patel, Glenn Reinman
    ParallAX: an architecture for real-time physics. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:232-243 [Conf]
  27. Vasily G. Moshnyaga, Hua Vo, Glenn Reinman, Miodrag Potkonjak
    Reducing Energy of DRAM/Flash Memory System by OS-controlled Data Refresh. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2108-2111 [Conf]
  28. Jason Cong, Guoling Han, Ashok Jagannathan, Glenn Reinman, Krzysztof Rutkowski
    Accelerating Sequential Applications on CMPs Using Core Spilling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2007, v:18, n:8, pp:1094-1107 [Journal]

  29. Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning. [Citation Graph (, )][DBLP]

  30. ACES: application-specific cycle elimination and splitting for deadlock-free routing on irregular network-on-chip. [Citation Graph (, )][DBLP]

  31. CMP network-on-chip overlaid with multi-band RF-interconnect. [Citation Graph (, )][DBLP]

  32. MC-Sim: an efficient simulation tool for MPSoC designs. [Citation Graph (, )][DBLP]

  33. Fine grain 3D integration for microarchitecture design through cube packing exploration. [Citation Graph (, )][DBLP]

  34. RF interconnects for communications on-chip. [Citation Graph (, )][DBLP]

  35. The Art of Deception: Adaptive Precision Reduction for Area Efficient Physics Acceleration. [Citation Graph (, )][DBLP]

  36. Power reduction of CMP communication networks via RF-interconnects. [Citation Graph (, )][DBLP]

  37. A scalable micro wireless interconnect structure for CMPs. [Citation Graph (, )][DBLP]

  38. Multiband RF-interconnect for reconfigurable network-on-chip communications. [Citation Graph (, )][DBLP]

  39. SteerBug: an interactive framework for specifying and detecting steering behaviors. [Citation Graph (, )][DBLP]

  40. Watch Out! A Framework for Evaluating Steering Behaviors. [Citation Graph (, )][DBLP]

  41. An Open Framework for Developing, Evaluating, and Sharing Steering Algorithms. [Citation Graph (, )][DBLP]

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