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David Zhigang Pan: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jason Cong, David Zhigang Pan
    Interconnect Delay Estimation Models for Synthesis and Design Planning. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:97-100 [Conf]
  2. Jason Cong, David Zhigang Pan, Prasanna V. Srinivas
    Improved crosstalk modeling for noise constrained interconnect optimization. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:373-378 [Conf]
  3. Jason Cong, David Zhigang Pan
    Interconnect Estimation and Dlanning for Deep Submicron Designs. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:507-510 [Conf]
  4. Joydeep Mitra, Peng Yu, David Zhigang Pan
    RADAR: RET-aware detailed routing using fast lithography simulations. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:369-372 [Conf]
  5. Haoxing Ren, David Zhigang Pan, Charles J. Alpert, Paul Villarrubia
    Diffusion-based placement migration. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:515-520 [Conf]
  6. Jason Cong, Lei He, Cheng-Kok Koh, David Zhigang Pan
    Global interconnect sizing and spacing with consideration of coupling capacitance. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:628-633 [Conf]
  7. Jason Cong, Tianming Kong, David Zhigang Pan
    Buffer block planning for interconnect-driven floorplanning. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:358-363 [Conf]
  8. Jason Cong, David Zhigang Pan, Lei He, Cheng-Kok Koh, Kei-Yong Khoo
    Interconnect design for deep submicron ICs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:478-485 [Conf]
  9. Tao Luo, Haoxing Ren, Charles J. Alpert, David Zhigang Pan
    Computational geometry based placement migration. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:41-47 [Conf]
  10. Haoxing Ren, David Zhigang Pan, Paul Villarrubia
    True crosstalk aware incremental placement with noise map. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:402-409 [Conf]
  11. Chin-Chih Chang, Jason Cong, David Zhigang Pan
    Physical hierarchy generation with routing congestion control. [Citation Graph (0, 0)][DBLP]
    ISPD, 2002, pp:36-41 [Conf]
  12. Haoxing Ren, David Zhigang Pan, David S. Kung
    Sensitivity guided net weighting for placement driven synthesis. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:10-17 [Conf]
  13. Chin-Chih Chang, Jason Cong, David Zhigang Pan, Xin Yuan
    Multilevel global placement with congestion control. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:4, pp:395-409 [Journal]
  14. Jason Cong, Lei He, Cheng-Kok Koh, David Zhigang Pan
    Interconnect sizing and spacing with consideration of couplingcapacitance. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:9, pp:1164-1169 [Journal]
  15. Jason Cong, David Zhigang Pan
    Interconnect performance estimation models for design planning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:6, pp:739-752 [Journal]
  16. Jason Cong, David Zhigang Pan
    Wire width planning for interconnect performance optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:3, pp:319-329 [Journal]
  17. Haoxing Ren, David Zhigang Pan, David S. Kung
    Sensitivity guided net weighting for placement-driven synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:5, pp:711-721 [Journal]

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