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Michail Romesis: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jason Cong, Michail Romesis, Joseph R. Shinnerl
    Fast floorplanning by look-ahead enabled recursive bipartitioning. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1119-1122 [Conf]
  2. Ashok Jagannathan, Hannah Honghua Yang, Kris Konigsfeld, Dan Milliron, Mosur Mohan, Michail Romesis, Glenn Reinman, Jason Cong
    Microarchitecture evaluation with floorplanning and interconnect pipelining. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:8-15 [Conf]
  3. Jason Cong, Ashok Jagannathan, Glenn Reinman, Michail Romesis
    Microarchitecture evaluation with physical planning. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:32-35 [Conf]
  4. Jason Cong, Michail Romesis
    Performance-Driven Multi-Level Clustering with Application to Hierarchical FPGA Mapping. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:389-394 [Conf]
  5. Jason Cong, Michail Romesis, Joseph R. Shinnerl
    Robust mixed-size placement under tight white-space constraints. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:165-172 [Conf]
  6. Jason Cong, Michail Romesis, Min Xie
    Optimality and Stability Study of Timing-Driven Placement Algorithms. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:472-479 [Conf]
  7. Jason Cong, Gabriele Nataneli, Michail Romesis, Joseph R. Shinnerl
    An area-optimality study of floorplanning. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:78-83 [Conf]
  8. Jason Cong, Michail Romesis, Min Xie
    Optimality, scalability and stability study of partitioning and placement algorithms. [Citation Graph (0, 0)][DBLP]
    ISPD, 2003, pp:88-94 [Conf]
  9. Tony F. Chan, Jason Cong, Michail Romesis, Joseph R. Shinnerl, Kenton Sze, Min Xie
    mPL6: a robust multilevel mixed-size placement engine. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:227-229 [Conf]
  10. Chin-Chih Chang, Jason Cong, Michail Romesis, Min Xie
    Optimality and scalability study of existing placement algorithms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:4, pp:537-549 [Journal]
  11. Jason Cong, Michail Romesis, Joseph R. Shinnerl
    Fast floorplanning by look-ahead enabled recursive bipartitioning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:9, pp:1719-1732 [Journal]

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