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Joseph R. Shinnerl: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jason Cong, Michail Romesis, Joseph R. Shinnerl
    Fast floorplanning by look-ahead enabled recursive bipartitioning. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1119-1122 [Conf]
  2. Tony Chan, Jason Cong, Tianming Kong, Joseph R. Shinnerl
    Multilevel Optimization for Large-Scale Circuit Placement. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:171-176 [Conf]
  3. Tony F. Chan, Jason Cong, Tim Kong, Joseph R. Shinnerl, Kenton Sze
    An Enhanced Multilevel Algorithm for Circuit Placement. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:299-306 [Conf]
  4. Jason Cong, Tim Kong, Joseph R. Shinnerl, Min Xie, Xin Yuan
    Large-Scale Circuit Placement: Gap and Promise. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:883-890 [Conf]
  5. Jason Cong, Michail Romesis, Joseph R. Shinnerl
    Robust mixed-size placement under tight white-space constraints. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:165-172 [Conf]
  6. Jason Cong, Gabriele Nataneli, Michail Romesis, Joseph R. Shinnerl
    An area-optimality study of floorplanning. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:78-83 [Conf]
  7. Tony F. Chan, Jason Cong, Michail Romesis, Joseph R. Shinnerl, Kenton Sze, Min Xie
    mPL6: a robust multilevel mixed-size placement engine. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:227-229 [Conf]
  8. Tony F. Chan, Jason Cong, Joseph R. Shinnerl, Kenton Sze, Min Xie
    mPL6: enhanced multilevel mixed-size placement. [Citation Graph (0, 0)][DBLP]
    ISPD, 2006, pp:212-214 [Conf]
  9. Jason Cong, Michail Romesis, Joseph R. Shinnerl
    Fast floorplanning by look-ahead enabled recursive bipartitioning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:9, pp:1719-1732 [Journal]
  10. Jason Cong, Joseph R. Shinnerl, Min Xie, Tim Kong, Xin Yuan
    Large-scale circuit placement. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:2, pp:389-430 [Journal]

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