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Fabrizio Ferrandi: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Roberto Cordone, Fabrizio Ferrandi, Marco D. Santambrogio, Gianluca Palermo, Donatella Sciuto
    Using speculative computation and parallelizing techniques to improve scheduling of control based designs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:898-904 [Conf]
  2. Fabrizio Ferrandi, Franco Fummi, Enrico Macii, Massimo Poncino, Donatella Sciuto
    Symbolic Optimization of FSM Networks Based on Sequential ATPG Techniques. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:467-470 [Conf]
  3. Francesco Bruschi, Michele Chiamenti, Fabrizio Ferrandi, Donatella Sciuto
    Error Simulation Based on the SystemC Design Description Language. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1135- [Conf]
  4. Francesco Bruschi, Fabrizio Ferrandi
    Synthesis of Complex Control Structures from Behavioral SystemC Models. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:20112-20119 [Conf]
  5. Roberto Cordone, Fabrizio Ferrandi, Donatella Sciuto, Roberto Wolfler Calvo
    An Efficient Heuristic Approach to Solve the Unate Covering Problem. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:364-371 [Conf]
  6. Fabrizio Ferrandi, Franco Fummi, Luca Gerli, Donatella Sciuto
    Symbolic Functional Vector Generation for VHDL Specifications. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:442-0 [Conf]
  7. Fabrizio Ferrandi, Franco Fummi, Enrico Macii, Massimo Poncino
    Power Estimation of Behavioral Descriptions. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:762-766 [Conf]
  8. Fabrizio Ferrandi, G. Ferrara, Donatella Sciuto, Alessandro Fin, Franco Fummi
    Functional test generation for behaviorally sequential models. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:403-410 [Conf]
  9. Fabrizio Ferrandi, Michele Rendine, Donatella Sciuto
    Functional Verification for SystemC Descriptions Using Constraint Solving. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:744-751 [Conf]
  10. Fabrizio Ferrandi, Pier Luca Lanzi, Donatella Sciuto, Mara Tanelli
    System-level metrics for hardware/software architectural mapping. [Citation Graph (0, 0)][DBLP]
    DELTA, 2004, pp:231-236 [Conf]
  11. Marco Brera, Fabrizio Ferrandi, Donatella Sciuto, Franco Fummi
    Increase the Behavioral Fault Model Accuracy Using High-Level Synthesis Information. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:174-180 [Conf]
  12. Massimo Bombana, Giacomo Buonanno, Patrizia Cavalloro, Fabrizio Ferrandi, Donatella Sciuto, Giuseppe Zaza
    Reduction of Fault Detection Costs through Testable Design of Sequential Architectures with Signal Feedbacks. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:223-230 [Conf]
  13. G. Biasoli, Fabrizio Ferrandi, Donatella Sciuto, Alessandro Fin, Franco Fummi
    BIST Architectures Selection Based on Behavioral Testing. [Citation Graph (0, 0)][DBLP]
    DFT, 2000, pp:292-298 [Conf]
  14. Fabrizio Ferrandi, Franco Fummi, Laura Pozzi, Mariagiovanna Sami
    Configuration-Specific Test Pattern Extraction for Field Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:85-93 [Conf]
  15. Carlo Amicucci, Fabrizio Ferrandi, Marco D. Santambrogio, Donatella Sciuto
    SyCERS: a SystemC Design Exploration Framework for SoC Reconfigurable Architecture. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:63-69 [Conf]
  16. Alberto Donato, Fabrizio Ferrandi, Massimo Redaelli, Marco D. Santambrogio, Donatella Sciuto
    Caronte: A Complete Methodology for the Implementation of Partially Dynamically Self-Reconfiguring Systems on FPGA Platforms. [Citation Graph (0, 0)][DBLP]
    FCCM, 2005, pp:321-322 [Conf]
  17. Fabrizio Ferrandi, Pier Luca Lanzi, Donatella Sciuto
    System Level Hardware-Software Design Exploration with XCS. [Citation Graph (0, 0)][DBLP]
    GECCO (2), 2004, pp:763-773 [Conf]
  18. F. S. Bietti, Fabrizio Ferrandi, Franco Fummi, Donatella Sciuto
    VHDL Testability Analysis Based on Fault Clustering and Implicit Fault Injection. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1998, pp:237-242 [Conf]
  19. Giacomo Buonanno, Fabrizio Ferrandi, L. Ferrandi, Franco Fummi, Donatella Sciuto
    How an "Evolving" Fault Model Improves the Behavioral Test Generation. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1997, pp:124-0 [Conf]
  20. Fabrizio Ferrandi, Franco Fummi, Enrico Macii, Massimo Poncino, Donatella Sciuto
    Test Generation for Networks of Interacting FSMs Using Symbolic Techniques. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1996, pp:208-213 [Conf]
  21. Antonino Tumeo, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto
    A design kit for a fully working shared memory multiprocessor on FPGA. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:219-222 [Conf]
  22. Fabrizio Ferrandi, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi, Fabio Somenzi
    Symbolic algorithms for layout-oriented synthesis of pass transistor logic circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:235-241 [Conf]
  23. M. Bacis, Giacomo Buonanno, Fabrizio Ferrandi, Franco Fummi, Luca Gerli, Donatella Sciuto
    Application of a Testing Framework to VHDL Descriptions at Different Abstraction Levels. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:654-658 [Conf]
  24. Roberto Bevacqua, Luca Guerrazzi, Fabrizio Ferrandi, Franco Fummi
    Implicit Test Sequences Compaction for Decreasing Test Application Cos. [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:384-382 [Conf]
  25. Fabrizio Ferrandi, Donatella Sciuto, Alessandro Fin, Franco Fummi
    An Application of Genetic Algorithms and BDDs to Functional Testing. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:48-0 [Conf]
  26. Fabrizio Ferrandi, Marco D. Santambrogio, Donatella Sciuto
    A Design Methodology for Dynamic Reconfiguration: The Caronte Architecture. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  27. Fabrizio Ferrandi, G. Ferrara, R. Palazzo, Vincenzo Rana, Marco D. Santambrogio
    VHDL to FPGA automatic IP-Core generation: a case study on Xilinx design flow. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  28. Giacomo Buonanno, Fabrizio Ferrandi, Donatella Sciuto
    Data Path Testability Analysis Based on BDDs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:2012-2014 [Conf]
  29. Angelo P. E. Rosiello, Fabrizio Ferrandi, Davide Pandini, Donatella Sciuto
    A Hash-based Approach for Functional Regularity Extraction During Logic Synthesis. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:92-97 [Conf]
  30. Antonino Tumeo, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto
    A Pipelined Fast 2D-DCT Accelerator for FPGA-based SoCs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:331-336 [Conf]
  31. Antonino Tumeo, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto
    An Internal Partial Dynamic Reconfiguration Implementation of the JPEG Encoder for Low-Cost FPGAsb. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:449-450 [Conf]
  32. S. Corbetta, Fabrizio Ferrandi, M. Morandi, M. Novati, Marco D. Santambrogio, Donatella Sciuto
    Two Novel Approaches to Online Partial Bitstream Relocation in a Dynamically Reconfigurable System. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:457-458 [Conf]
  33. Fabrizio Ferrandi, Franco Fummi, Donatella Sciuto
    Implicit test generation for behavioral VHDL models. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:587-0 [Conf]
  34. Tiziana Gravagnoli, Fabrizio Ferrandi, Pier Luca Lanzi, Donatella Sciuto
    Automatic Test Pattern Generation with BOA. [Citation Graph (0, 0)][DBLP]
    PPSN, 2006, pp:423-432 [Conf]
  35. Massimo Bombana, Giacomo Buonanno, Patrizia Cavalloro, Fabrizio Ferrandi, Donatella Sciuto, Giuseppe Zaza
    An Expert Solution to Functional Testability Analysis of VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    SEKE, 1993, pp:263-265 [Conf]
  36. Fabrizio Ferrandi, G. Fornara, Donatella Sciuto, G. Ferrara, Franco Fummi
    Testability Alternatives Exploration through Functional Testing. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:423-430 [Conf]
  37. Fabrizio Ferrandi, Franco Fummi, Donatella Sciuto, Enrico Macii, Massimo Poncino
    Testing Core-Based Systems: A Symbolic Methodology. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1997, v:14, n:4, pp:69-77 [Journal]
  38. Francesco Bruschi, Fabrizio Ferrandi, Donatella Sciuto
    A Framework for the Functional Verification of SystemC Models. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2005, v:33, n:6, pp:667-695 [Journal]
  39. Anna Antola, Fabrizio Ferrandi, Vincenzo Piuri, Mariagiovanna Sami
    Semiconcurrent Error Detection in Data Paths. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:5, pp:449-465 [Journal]
  40. Fabrizio Ferrandi, Franco Fummi, Donatella Sciuto
    Test Generation and Testability Alternatives Exploration of Critical Algorithms for Embedded Applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2002, v:51, n:2, pp:200-215 [Journal]
  41. Roberto Cordone, Fabrizio Ferrandi, Donatella Sciuto, Roberto Wolfler Calvo
    An efficient heuristic approach to solve the unate covering problem. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:12, pp:1377-1388 [Journal]
  42. Fabrizio Ferrandi, Franco Fummi, Enrico Macii, Massimo Poncino, Donatella Sciuto
    Symbolic optimization of interacting controllers based onredundancy identification and removal. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:7, pp:760-772 [Journal]
  43. Fabrizio Ferrandi, Pier Luca Lanzi, Gianluca Palermo, Christian Pilato, Donatella Sciuto, Antonino Tumeo
    An Evolutionary Approach to Area-Time Optimization of FPGA designs. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:145-152 [Conf]
  44. Simone Borgio, Davide Bosisio, Fabrizio Ferrandi, Matteo Monchiero, Marco D. Santambrogio, Donatella Sciuto, Antonino Tumeo
    Hardware DWT accelerator for MultiProcessor System-on-Chip on FPGA. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2006, pp:107-114 [Conf]
  45. Antonino Tumeo, Marco Branca, Lorenzo Camerini, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto
    An Interrupt Controller for FPGA-based Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:82-87 [Conf]
  46. Alberto Donato, Fabrizio Ferrandi, Massimo Redaelli, Marco D. Santambrogio, Donatella Sciuto
    Caronte: A methodology for the Implementation of Partially dynamically Self-Reconfiguring Systems on FPGA Platforms. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2005, pp:87-109 [Conf]
  47. Fabrizio Ferrandi, Luca Fossati, Marco Lattuada, Gianluca Palermo, Donatella Sciuto, Antonino Tumeo
    Automatic Parallelization of Sequential Specifications for Symmetric MPSoCs. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:179-192 [Conf]
  48. Fabrizio Ferrandi, Franco Fummi, Graziano Pravadelli, Donatella Sciuto
    Identification of design errors through functional testing. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Reliability, 2003, v:52, n:4, pp:400-412 [Journal]
  49. Massimo Bombana, Giacomo Buonanno, Patrizia Cavalloro, Fabrizio Ferrandi, Donatella Sciuto, Giuseppe Zaza
    ALADIN: a multilevel testability analyzer for VLSI system design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:2, pp:157-171 [Journal]

  50. Combining Target-independent Analysis with Dynamic Profiling to Build the Performance Model of a DSP. [Citation Graph (, )][DBLP]


  51. A Self-Reconfigurable Implementation of the JPEG Encoder. [Citation Graph (, )][DBLP]


  52. Lightweight DMA management mechanisms for multiprocessors on FPGA. [Citation Graph (, )][DBLP]


  53. Prototyping pipelined applications on a heterogeneous FPGA multiprocessor virtual platform. [Citation Graph (, )][DBLP]


  54. Mapping pipelined applications onto heterogeneous embedded systems: a bayesian optimization algorithm based approach. [Citation Graph (, )][DBLP]


  55. A Dual-Priority Real-Time Multiprocessor System on FPGA for Automotive Applications. [Citation Graph (, )][DBLP]


  56. A reconfigurable multiprocessor architecture for a reliable face recognition implementation. [Citation Graph (, )][DBLP]


  57. HW/SW methodologies for synchronization in FPGA multiprocessors. [Citation Graph (, )][DBLP]


  58. Evolutionary algorithms for the mapping of pipelined applications onto heterogeneous embedded systems. [Citation Graph (, )][DBLP]


  59. Multiprocessor systems-on-chip synthesis using multi-objective evolutionary computation. [Citation Graph (, )][DBLP]


  60. A multiprocessor self-reconfigurable JPEG2000 encoder. [Citation Graph (, )][DBLP]


  61. hArtes design flow for heterogeneous platforms. [Citation Graph (, )][DBLP]


  62. A Multi-objective Genetic Algorithm for Design Space Exploration in High-Level Synthesis. [Citation Graph (, )][DBLP]


  63. Ant colony optimization for mapping and scheduling in heterogeneous multiprocessor systems. [Citation Graph (, )][DBLP]


  64. Fitness inheritance in evolutionary and multi-objective high-level synthesis. [Citation Graph (, )][DBLP]


  65. High-level synthesis with multi-objective genetic algorithm: A comparative encoding analysis. [Citation Graph (, )][DBLP]


  66. A SystemC-based Framework of Communication Architecture. [Citation Graph (, )][DBLP]


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