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Marco D. Santambrogio: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Roberto Cordone, Fabrizio Ferrandi, Marco D. Santambrogio, Gianluca Palermo, Donatella Sciuto
    Using speculative computation and parallelizing techniques to improve scheduling of control based designs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:898-904 [Conf]
  2. Giovanni Agosta, Francesco Bruschi, Marco D. Santambrogio, Donatella Sciuto
    Synthesis of Object Oriented Models on Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:249-250 [Conf]
  3. Carlo Amicucci, Fabrizio Ferrandi, Marco D. Santambrogio, Donatella Sciuto
    SyCERS: a SystemC Design Exploration Framework for SoC Reconfigurable Architecture. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:63-69 [Conf]
  4. Giovanni Agosta, Francesco Bruschi, Marco D. Santambrogio, Donatella Sciuto
    A Data Oriented Approach to the Design of Reconfigurable Stream Decoders. [Citation Graph (0, 0)][DBLP]
    ESTImedia, 2005, pp:107-112 [Conf]
  5. Alberto Donato, Fabrizio Ferrandi, Massimo Redaelli, Marco D. Santambrogio, Donatella Sciuto
    Caronte: A Complete Methodology for the Implementation of Partially Dynamically Self-Reconfiguring Systems on FPGA Platforms. [Citation Graph (0, 0)][DBLP]
    FCCM, 2005, pp:321-322 [Conf]
  6. Cristiana Bolchini, Davide Quarta, Marco D. Santambrogio
    SEU mitigation for sram-based fpgas through dynamic partial reconfiguration. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:55-60 [Conf]
  7. Fabrizio Ferrandi, Marco D. Santambrogio, Donatella Sciuto
    A Design Methodology for Dynamic Reconfiguration: The Caronte Architecture. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  8. Fabrizio Ferrandi, G. Ferrara, R. Palazzo, Vincenzo Rana, Marco D. Santambrogio
    VHDL to FPGA automatic IP-Core generation: a case study on Xilinx design flow. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  9. S. Corbetta, Fabrizio Ferrandi, M. Morandi, M. Novati, Marco D. Santambrogio, Donatella Sciuto
    Two Novel Approaches to Online Partial Bitstream Relocation in a Dynamically Reconfigurable System. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:457-458 [Conf]
  10. Marco D. Santambrogio, Donatella Sciuto
    Partial Dynamic Reconfiguration: The Caronte Approach. A New Degree of Freedom in the HW/SW Codesign. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-2 [Conf]
  11. Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto, Boris Kettelhoit, Markus Köster, Mario Porrmann, Ulrich Rückert
    Partial Dynamic Reconfiguration in a Multi-FPGA Clustered Architecture Based on Linux. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-8 [Conf]
  12. Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto
    Dynamic Reconfigurability in Embedded System Design. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2734-2737 [Conf]
  13. Simone Borgio, Davide Bosisio, Fabrizio Ferrandi, Matteo Monchiero, Marco D. Santambrogio, Donatella Sciuto, Antonino Tumeo
    Hardware DWT accelerator for MultiProcessor System-on-Chip on FPGA. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2006, pp:107-114 [Conf]
  14. Matteo Murgida, Alessandro Panella, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto
    Fast IP-Core Generation in a Partial Dynamic Reconfiguration Workflow. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:74-79 [Conf]
  15. Marco Giorgetta, Marco D. Santambrogio, Donatella Sciuto, Paola Spoletini
    A graph-coloring approach to the allocation and tasks scheduling for reconfigurable architectures. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:24-29 [Conf]
  16. Alberto Donato, Fabrizio Ferrandi, Massimo Redaelli, Marco D. Santambrogio, Donatella Sciuto
    Caronte: A methodology for the Implementation of Partially dynamically Self-Reconfiguring Systems on FPGA Platforms. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2005, pp:87-109 [Conf]

  17. An application-centered design flow for self reconfigurable systems implementation. [Citation Graph (, )][DBLP]


  18. The Shining embedded system design methodology based on self dynamic reconfigurable architectures. [Citation Graph (, )][DBLP]


  19. Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems. [Citation Graph (, )][DBLP]


  20. An adaptable FPGA-based System for Regular Expression Matching. [Citation Graph (, )][DBLP]


  21. Task Scheduling with Configuration Prefetching and Anti-Fragmentation techniques on Dynamically Reconfigurable Systems. [Citation Graph (, )][DBLP]


  22. A Requirements-Driven Reconfigurable SoC Communication Infrastructure Design Flow. [Citation Graph (, )][DBLP]


  23. A Design Workflow for the Identification of Area Constraints in Dynamic Reconfigurable Systems. [Citation Graph (, )][DBLP]


  24. A Generation Flow for Self-Reconfiguration Controllers Customization. [Citation Graph (, )][DBLP]


  25. TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs. [Citation Graph (, )][DBLP]


  26. Exploring Partial Reconfiguration for Mitigating SEU faults in SRAM-Based FPGAs. [Citation Graph (, )][DBLP]


  27. Task Partitioning for the Scheduling on Reconfigurable Systems driven by Specification Self-Similarity. [Citation Graph (, )][DBLP]


  28. Evolvable Hardware: A Functional Level Evolution Framework Based on ImpulseC. [Citation Graph (, )][DBLP]


  29. SiLLis: A Simplified Language for Monitoring and Debugging of Reconfigurable Systems. [Citation Graph (, )][DBLP]


  30. Operating system support for online partial dynamic reconfiguration management. [Citation Graph (, )][DBLP]


  31. A runtime relocation based workflow for self dynamic reconfigurable systems design. [Citation Graph (, )][DBLP]


  32. Reconfigurable NoC design flow for multiple applications run-time mapping on FPGA devices. [Citation Graph (, )][DBLP]


  33. Task graph scheduling for reconfigurable architectures driven by reconfigurations hiding and resources reuse. [Citation Graph (, )][DBLP]


  34. A novel SoC design methodology combining adaptive software and reconfigurable hardware. [Citation Graph (, )][DBLP]


  35. A design flow tailored for self dynamic reconfigurable architecture. [Citation Graph (, )][DBLP]


  36. Design methodology for partial dynamic reconfiguration: a new degree of freedom in the HW/SW codesign. [Citation Graph (, )][DBLP]


  37. HARPE: A Harvard-based processing element tailored for partial dynamic reconfigurable architectures. [Citation Graph (, )][DBLP]


  38. On-line task management for a reconfigurable cryptographic architecture. [Citation Graph (, )][DBLP]


  39. Core Allocation and Relocation Management for a Self Dynamically Reconfigurable Architecture. [Citation Graph (, )][DBLP]


  40. Application heartbeats for software performance and health. [Citation Graph (, )][DBLP]


  41. A light-weight Network-on-Chip architecture for dynamically reconfigurable systems. [Citation Graph (, )][DBLP]


  42. ReCPU: A parallel and pipelined architecture for regular expression matching. [Citation Graph (, )][DBLP]


  43. An adaptive genetic algorithm for dynamically reconfigurable modules allocation. [Citation Graph (, )][DBLP]


  44. From Reconfigurable Architectures to Self-Adaptive Autonomic Systems. [Citation Graph (, )][DBLP]


  45. A Requirements-Driven Simulation Framework for Communication Infrastructures Design. [Citation Graph (, )][DBLP]


  46. Adaptive Metrics for System-Level Functional Partitioning. [Citation Graph (, )][DBLP]


  47. An ILP Formulation for the Task Graph Scheduling Problem Tailored to Bi-dimensional Reconfigurable Architectures. [Citation Graph (, )][DBLP]


  48. A Reconfiguration-Aware Floorplacer for FPGAs. [Citation Graph (, )][DBLP]


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