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Publications of Author

1. Philip Brisk, Ajay K. Verma, Paolo Ienne, Hadi Parandeh-Afshar
   Enhancing FPGA Performance for Arithmetic Circuits. [Citation Graph (0, 0)][DBLP]
   DAC, 2007, pp:334-337 [Conf]
   
2. Hadi Parandeh-Afshar, Ali Afzali-Kusha, Ali Khakifirooz
   A very high performance address BUS encoder. [Citation Graph (0, 0)][DBLP]
   ISCAS, 2006, pp:- [Conf]
   
3. 
   Efficient synthesis of compressor trees on FPGAs. [Citation Graph (, )][DBLP]
   
   
4. 
   Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming. [Citation Graph (, )][DBLP]
   
   
5. 
   Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs. [Citation Graph (, )][DBLP]
   
   
6. 
   A novel FPGA logic block for improved arithmetic performance. [Citation Graph (, )][DBLP]
   
   
7. 
   3D configuration caching for 2D FPGAs. [Citation Graph (, )][DBLP]
   
   
8. 
   Exploiting fast carry-chains of FPGAs for designing compressor trees. [Citation Graph (, )][DBLP]
   
   
9. 
   Using 3D integration technology to realize multi-context FPGAs. [Citation Graph (, )][DBLP]