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Sharad C. Seth: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. George Nagy, Sharad C. Seth, Mahesh Viswanathan
    A Prototype Document Image Analysis System for Technical Journals. [Citation Graph (2, 0)][DBLP]
    IEEE Computer, 1992, v:25, n:7, pp:10-22 [Journal]
  2. Hailong Cui, Sharad C. Seth, Shashank K. Mehta
    A Novel Method to Improve the Test Efficiency of VLSI Tests. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:499-504 [Conf]
  3. Kent L. Einspahr, Shashank K. Mehta, Sharad C. Seth
    Synthesis of Sequential Circuits with Clock Control to Improve Testability. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:472-0 [Conf]
  4. Sheng Zhang, Sharad C. Seth, Bhargab B. Bhattacharya
    Efficient Test Compaction for Pseudo-Random Testing. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:337-342 [Conf]
  5. Stephen D. Scott, Ashok Samal, Sharad C. Seth
    HGA: A Hardware-Based Genetic Algorithm. [Citation Graph (0, 0)][DBLP]
    FPGA, 1995, pp:53-59 [Conf]
  6. Vishwani D. Agrawal, Sharad C. Seth
    Mutually Disjoint Signals and Probability Calculation in Digital Circuits. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1998, pp:307-312 [Conf]
  7. Kent L. Einspahr, Sharad C. Seth, Vishwani D. Agrawal
    Improving Circuit Testability by Clock Control. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1996, pp:288-293 [Conf]
  8. George Nagy, Ashok Samal, Sharad C. Seth, T. Fisher, E. Guthmann, K. Kalafala, Luyang Li, Prateek Sarkar, S. Sivasubramaniam, Yihong Xu
    A Prototype for Adaptive Association of Street Names with Streets on Maps. [Citation Graph (0, 0)][DBLP]
    GREC, 1997, pp:302-313 [Conf]
  9. Luyang Li, George Nagy, Ashok Samal, Sharad C. Seth, Yihong Xu
    Cooperative Text and Line-Art Extraction from a Topographic Map. [Citation Graph (0, 0)][DBLP]
    ICDAR, 1999, pp:467-470 [Conf]
  10. Don Sylwester, Sharad C. Seth
    Adaptive Segmentation of Document Images. [Citation Graph (0, 0)][DBLP]
    ICDAR, 2001, pp:827-831 [Conf]
  11. Don Sylwester, Sharad C. Seth
    A trainable, single-pass algorithm for column segmentation. [Citation Graph (0, 0)][DBLP]
    ICDAR, 1995, pp:615-618 [Conf]
  12. Yuhong Yu, Ashok Samal, Sharad C. Seth
    A system for recognizing a large class of engineering drawings. [Citation Graph (0, 0)][DBLP]
    ICDAR, 1995, pp:791-794 [Conf]
  13. Ashutosh Joshi, George Nagy, Daniel P. Lopresti, Sharad C. Seth
    A Maximum-Likelihood Approach to Symbolic Indirect Correlation. [Citation Graph (0, 0)][DBLP]
    ICPR (3), 2006, pp:99-103 [Conf]
  14. Bhargab B. Bhattacharya, Sharad C. Seth, Sheng Zhang
    Double-Tree Scan: A Novel Low-Power Scan-Path Architecture. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:470-479 [Conf]
  15. Dharam Vir Das, Sharad C. Seth, Vishwani D. Agrawal
    Estimating the Quality of Manufactured Digital Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:210-217 [Conf]
  16. Raghu V. Hudli, Sharad C. Seth
    Testability Analysis of Synchronous Sequential Circuits Based on Structural Data. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:364-372 [Conf]
  17. Sharad C. Seth
    Predicting Fault Coverage from Probabilistic Testability. [Citation Graph (0, 0)][DBLP]
    ITC, 1985, pp:803-807 [Conf]
  18. Mark W. Weiss, Sharad C. Seth, Shashank K. Mehta, Kent L. Einspahr
    Exploiting don't cares to enhance functional tests. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:538-546 [Conf]
  19. Paul Kenyon, Prathima Agrawal, Sharad C. Seth
    High-level microprogramming: an optimizing C compiler for a processing element of a CAD accelerator. [Citation Graph (0, 0)][DBLP]
    MICRO, 1990, pp:97-106 [Conf]
  20. Bhargab B. Bhattacharya, Sharad C. Seth, Sheng Zhang
    Low-Energy BIST Design for Scan-based Logic Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:546-551 [Conf]
  21. Hailong Cui, Sharad C. Seth, Shashank K. Mehta
    A Novel Method to Improve the Test Efficiency of VLSI Tests. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:499-504 [Conf]
  22. Shashank K. Mehta, Kent L. Einspahr, Sharad C. Seth
    Synthesis for Testability by Two-Clock Control. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:279-283 [Conf]
  23. Shashank K. Mehta, Sharad C. Seth
    Empirical Computation of Reject Ratio in VLSI Testing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:506-511 [Conf]
  24. Sharad C. Seth, Lee Gowen, Matt Payne, Don Sylwester
    Logic Simulation Using an Asynchronous Parallel Discrete-Event Simulation Model on a SIMD Machine. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:29-32 [Conf]
  25. S. Venkatraman, Sharad C. Seth, Prathima Agrawal
    Parallel test generation with low communication overhead. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:116-120 [Conf]
  26. Sheng Zhang, Sharad C. Seth, Bhargab B. Bhattacharya
    On Finding Consecutive Test Vectors in a Random Sequence for Energy-Aware BIST Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:491-496 [Conf]
  27. Mark W. Weiss, Sharad C. Seth, Shashank K. Mehta, Kent L. Einspahr
    Design Verification and Functional Testing of FiniteState Machines. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:189-195 [Conf]
  28. Jian Kang, Sharad C. Seth, Vijay Gangaram
    Efficient RTL Coverage Metric for Functional Test Selection. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:318-324 [Conf]
  29. Prathima Agrawal, Vishwani D. Agrawal, Sharad C. Seth
    Generating Tests for Delay Faults in Nonscan Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1993, v:10, n:1, pp:20-28 [Journal]
  30. N. Ranganathan, Sharad C. Seth
    Conference Reports. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1995, v:12, n:2, pp:5- [Journal]
  31. Ashok Samal, Sharad C. Seth, Kevin Cueto
    A feature-based approach to conflation of geospatial sources. [Citation Graph (0, 0)][DBLP]
    International Journal of Geographical Information Science, 2004, v:18, n:5, pp:459-489 [Journal]
  32. Luyang Li, George Nagy, Ashok Samal, Sharad C. Seth, Yihong Xu
    Integrated text and line-art extraction from a topographic map. [Citation Graph (0, 0)][DBLP]
    IJDAR, 2000, v:2, n:4, pp:177-185 [Journal]
  33. James M. Steckelberg, Sharad C. Seth
    On a Relation Between Algebraic Programs and Turing Machines. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 1977, v:6, n:6, pp:180-183 [Journal]
  34. Mukkai S. Krishnamoorthy, George Nagy, Sharad C. Seth, Mahesh Viswanathan
    Syntactic Segmentation and Labeling of Digitized Pages from Technical Journals. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Pattern Anal. Mach. Intell., 1993, v:15, n:7, pp:737-747 [Journal]
  35. Yuhong Yu, Ashok Samal, Sharad C. Seth
    Isolating symbols from connection lines in a class of engineering drawings. [Citation Graph (0, 0)][DBLP]
    Pattern Recognition, 1994, v:27, n:3, pp:391-404 [Journal]
  36. Bhargab B. Bhattacharya, Sharad C. Seth
    Design of Parity Testable Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1989, v:38, n:11, pp:1580-1584 [Journal]
  37. Ten-Chuan Hsiao, Sharad C. Seth
    An Analysis of the Use of Rademacher-Walsh Spectrum in Compact Testing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1984, v:33, n:10, pp:934-937 [Journal]
  38. Kolar L. Kodandapani, Sharad C. Seth
    On Combinational Networks with Restricted Fan-Out. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1978, v:27, n:4, pp:309-318 [Journal]
  39. Lester Lipsky, Sharad C. Seth
    Signal Probabilities in AND-OR Trees. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1989, v:38, n:11, pp:1558-1563 [Journal]
  40. Sharad C. Seth, Lester Lipsky
    A Simplified Method to Calculate Failure Times in Fault-Tolerant Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1983, v:32, n:8, pp:754-760 [Journal]
  41. Sharad C. Seth, Vishwani D. Agrawal, Hassan Farhat
    A Statistical Theory of Digital Circuit Testability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:4, pp:582-586 [Journal]
  42. Sharad C. Seth, Kolar L. Kodandapani
    Diagnosis of Faults in Linear Tree Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1977, v:26, n:1, pp:29-33 [Journal]
  43. Sharad C. Seth, K. Narayanaswamy
    A Graph Model for Pattern-Sensitive Faults in Random Access Memories. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1981, v:30, n:12, pp:973-977 [Journal]
  44. Kent L. Einspahr, Shashank K. Mehta, Sharad C. Seth
    A synthesis for testability scheme for finite state machines using clock control. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:12, pp:1780-1792 [Journal]
  45. Sharad C. Seth, Vishwani D. Agrawal
    Characterizing the LSI Yield Equation from Wafer Test Data. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1984, v:3, n:2, pp:123-126 [Journal]
  46. D. Das, Sharad C. Seth, Vishwani D. Agrawal
    Accurate computation of field reject ratio based on fault latency. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:4, pp:537-545 [Journal]

  47. Analysis and taxonomy of column header categories for web tables. [Citation Graph (, )][DBLP]


  48. Interactive Conversion of Web Tables. [Citation Graph (, )][DBLP]


  49. Efficient Selection of Observation Points for Functional Tests. [Citation Graph (, )][DBLP]


  50. From Tessellations to Table Interpretation. [Citation Graph (, )][DBLP]


  51. A Unified Solution to Scan Test Volume, Time, and Power Minimization. [Citation Graph (, )][DBLP]


  52. A nonparametric classifier for unsegmented text. [Citation Graph (, )][DBLP]


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