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Shashank K. Mehta: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Hailong Cui, Sharad C. Seth, Shashank K. Mehta
    A Novel Method to Improve the Test Efficiency of VLSI Tests. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:499-504 [Conf]
  2. Kent L. Einspahr, Shashank K. Mehta, Sharad C. Seth
    Synthesis of Sequential Circuits with Clock Control to Improve Testability. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:472-0 [Conf]
  3. Ahmed M. Mahdy, Jitender S. Deogun, Shashank K. Mehta
    Broadband Optical Wireless Internet: Delay Optimization. [Citation Graph (0, 0)][DBLP]
    BROADNETS, 2004, pp:736-738 [Conf]
  4. Chandan K. Dubey, Shashank K. Mehta
    On Indecomposability Preserving Elimination Sequences. [Citation Graph (0, 0)][DBLP]
    COCOON, 2006, pp:42-51 [Conf]
  5. Chandan K. Dubey, Shashank K. Mehta, Jitender S. Deogun
    Conditionally Critical Indecomposable Graphs. [Citation Graph (0, 0)][DBLP]
    COCOON, 2005, pp:690-700 [Conf]
  6. Divesh Aggarwal, Chandan K. Dubey, Shashank K. Mehta
    Algorithms on Graphs with Small Dominating Targets. [Citation Graph (0, 0)][DBLP]
    ISAAC, 2006, pp:141-152 [Conf]
  7. Mark W. Weiss, Sharad C. Seth, Shashank K. Mehta, Kent L. Einspahr
    Exploiting don't cares to enhance functional tests. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:538-546 [Conf]
  8. Ahmed M. Mahdy, Jitender S. Deogun, Shashank K. Mehta
    End-to-End Delay Heuristics for Adaptive Optical Wireless Networks. [Citation Graph (0, 0)][DBLP]
    MASCOTS, 2004, pp:383-390 [Conf]
  9. Hailong Cui, Sharad C. Seth, Shashank K. Mehta
    A Novel Method to Improve the Test Efficiency of VLSI Tests. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:499-504 [Conf]
  10. Shashank K. Mehta, Kent L. Einspahr, Sharad C. Seth
    Synthesis for Testability by Two-Clock Control. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:279-283 [Conf]
  11. Shashank K. Mehta, Sharad C. Seth
    Empirical Computation of Reject Ratio in VLSI Testing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:506-511 [Conf]
  12. Mark W. Weiss, Sharad C. Seth, Shashank K. Mehta, Kent L. Einspahr
    Design Verification and Functional Testing of FiniteState Machines. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:189-195 [Conf]
  13. Divesh Aggarwal, Shashank K. Mehta, Jitender S. Deogun
    Domination Search on Graphs with Low Dominating-Target-Number. [Citation Graph (0, 0)][DBLP]
    WG, 2005, pp:28-37 [Conf]
  14. Shashank K. Mehta, Maharaj Mukherjee, George Nagy
    Constrained Integer Approximation to Planar Line Intersection. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 1991, v:40, n:3, pp:137-139 [Journal]
  15. Shashank K. Mehta, Laszlo Fulop
    An analog neural network to solve the hamiltonian cycle problem. [Citation Graph (0, 0)][DBLP]
    Neural Networks, 1993, v:6, n:6, pp:869-881 [Journal]
  16. Kent L. Einspahr, Shashank K. Mehta, Sharad C. Seth
    A synthesis for testability scheme for finite state machines using clock control. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:12, pp:1780-1792 [Journal]

  17. Implied Set Closure and Its Application to Memory Consistency Verification. [Citation Graph (, )][DBLP]


  18. Polynomial irreducibility testing through Minkowski summand computation. [Citation Graph (, )][DBLP]


  19. Generalized Reduction to Compute Toric Ideals. [Citation Graph (, )][DBLP]


  20. A nonparametric classifier for unsegmented text. [Citation Graph (, )][DBLP]


  21. Critically indecomposable graphs. [Citation Graph (, )][DBLP]


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