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## Search the dblp DataBase
Sunil P. Khatri:
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## Publications of Author- Van R. Culver, Sunil P. Khatri
**A dynamic voltage scaling algorithm for energy reduction in hard real-time systems.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2005, pp:842-845 [Conf] - Brock J. LaMeres, Kanupriya Gulati, Sunil P. Khatri
**Controlling inductive cross-talk and power in off-chip buses using CODECs.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2006, pp:850-855 [Conf] - Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards, Sunil P. Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa
**VIS: A System for Verification and Synthesis.**[Citation Graph (0, 0)][DBLP] CAV, 1996, pp:428-432 [Conf] - Rajesh Garg, Nikhil Jayakumar, Sunil P. Khatri, Gwan Choi
**A design approach for radiation-hard digital electronics.**[Citation Graph (0, 0)][DBLP] DAC, 2006, pp:773-778 [Conf] - Nikhil Jayakumar, Sandeep Dhar, Sunil P. Khatri
**A self-adjusting scheme to determine the optimum RBB by monitoring leakage currents.**[Citation Graph (0, 0)][DBLP] DAC, 2005, pp:43-46 [Conf] - Nikhil Jayakumar, Rajesh Garg, Bruce Gamache, Sunil P. Khatri
**A PLA based asynchronous micropipelining approach for subthreshold circuit design.**[Citation Graph (0, 0)][DBLP] DAC, 2006, pp:419-424 [Conf] - Nikhil Jayakumar, Sunil P. Khatri
**A variation tolerant subthreshold design approach.**[Citation Graph (0, 0)][DBLP] DAC, 2005, pp:716-719 [Conf] - Sunil P. Khatri, Amit Mehrotra, Robert K. Brayton, Ralph H. J. M. Otten, Alberto L. Sangiovanni-Vincentelli
**A Novel VLSI Layout Fabric for Deep Sub-Micron Applications.**[Citation Graph (0, 0)][DBLP] DAC, 1999, pp:491-496 [Conf] - Sunil P. Khatri, Amit Narayan, Sriram C. Krishnan, Kenneth L. McMillan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
**Engineering Change in a Non-Deterministic FSM Setting.**[Citation Graph (0, 0)][DBLP] DAC, 1996, pp:451-456 [Conf] - Nikhil Saluja, Sunil P. Khatri
**A robust algorithm for approximate compatible observability don't care (CODC) computation.**[Citation Graph (0, 0)][DBLP] DAC, 2004, pp:422-427 [Conf] - Chunjie Duan, Sunil P. Khatri
**Exploiting Crosstalk to Speed up On-Chip Buse.**[Citation Graph (0, 0)][DBLP] DATE, 2004, pp:778-783 [Conf] - Brock J. LaMeres, Sunil P. Khatri
**Encoding-Based Minimization of Inductive Cross-Talk for Off-Chip Data Transmission.**[Citation Graph (0, 0)][DBLP] DATE, 2005, pp:1318-1323 [Conf] - Brock J. LaMeres, Sunil P. Khatri
**Bus stuttering: an encoding technique to reduce inductive noise in off-chip data transmission.**[Citation Graph (0, 0)][DBLP] DATE, 2006, pp:522-527 [Conf] - Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards, Sunil P. Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa
**VIS.**[Citation Graph (0, 0)][DBLP] FMCAD, 1996, pp:248-256 [Conf] - Jawahar Jain, Amit Narayan, C. Coelho, Sunil P. Khatri, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton, Masahiro Fujita
**Decomposition Techniques for Efficient ROBDD Construction.**[Citation Graph (0, 0)][DBLP] FMCAD, 1996, pp:419-434 [Conf] - Scott J. Campbell, Sunil P. Khatri
**Resource and delay efficient matrix multiplication using newer FPGA devices.**[Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2006, pp:308-311 [Conf] - Rajesh Garg, Mario Sanchez, Kanupriya Gulati, Nikhil Jayakumar, Anshul Gupta, Sunil P. Khatri
**A design flow to optimize circuit delay by using standard cells and PLAs.**[Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2006, pp:217-222 [Conf] - Bo Shen, Sunil P. Khatri, Takis Zourntos
**Implementation of MOSFET based capacitors for digital applications.**[Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2006, pp:180-186 [Conf] - Wilsin Gosti, Sunil P. Khatri, Alberto L. Sangiovanni-Vincentelli
**Addressing the Timing Closure Problem by Integrating Logic Optimization and Placement.**[Citation Graph (0, 0)][DBLP] ICCAD, 2001, pp:224-231 [Conf] - Nikhil Jayakumar, Sunil P. Khatri
**A metal and via maskset programmable VLSI design methodology using PLAs.**[Citation Graph (0, 0)][DBLP] ICCAD, 2004, pp:590-594 [Conf] - A. Kapoor, Nikhil Jayakumar, Sunil P. Khatri
**A novel clock distribution and dynamic de-skewing methodology.**[Citation Graph (0, 0)][DBLP] ICCAD, 2004, pp:626-631 [Conf] - Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
**Cross-Talk Immune VLSI Design Using a Network of PLAs Embedded in a Regular Layout Fabric.**[Citation Graph (0, 0)][DBLP] ICCAD, 2000, pp:412-418 [Conf] - Ganesh Venkataraman, Nikhil Jayakumar, Jiang Hu, Peng Li, Sunil P. Khatri, Anand Rajaram, Patrick McGuinness, Charles J. Alpert
**Practical techniques to reduce skew and its variations in buffered clock networks.**[Citation Graph (0, 0)][DBLP] ICCAD, 2005, pp:592-596 [Conf] - Nikhil Jayakumar, Sunil P. Khatri, Kanupriya Gulati, Alexander Sprintson
**Network coding for routability improvement in VLSI.**[Citation Graph (0, 0)][DBLP] ICCAD, 2006, pp:820-823 [Conf] - Seraj Ahmad, Nikhil Jayakumar, Vijay Balasubramanian, Edward Hursey, Sunil P. Khatri, Rabi N. Mahapatra
**X-Routing using Two Manhattan Route Instances.**[Citation Graph (0, 0)][DBLP] ICCD, 2005, pp:45-52 [Conf] - Nikhil Jayakumar, Sunil P. Khatri
**Minimum Energy Near-threshold Network of PLA based Design.**[Citation Graph (0, 0)][DBLP] ICCD, 2005, pp:399-404 [Conf] - Brock J. LaMeres, Sunil P. Khatri
**Broadband Impedance Matching for Inductive Interconnect in VLSI Packages.**[Citation Graph (0, 0)][DBLP] ICCD, 2005, pp:683-688 [Conf] - Subarnarekha Sinha, Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
**Binary and Multi-Valued SPFD-Based Wire Removal in PLA Networks.**[Citation Graph (0, 0)][DBLP] ICCD, 2000, pp:494-503 [Conf] - Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri
**An algebraic decision diagram (ADD) based technique to find leakage histograms of combinational designs.**[Citation Graph (0, 0)][DBLP] ISLPED, 2005, pp:111-114 [Conf] - Nikhil Jayakumar, Sunil P. Khatri
**An ASIC design methodology with predictably low leakage, using leakage-immune standard cells.**[Citation Graph (0, 0)][DBLP] ISLPED, 2003, pp:128-133 [Conf] - Sabyasachi Das, Sunil P. Khatri
**A regularity-driven fast gridless detailed router for high frequency datapath designs.**[Citation Graph (0, 0)][DBLP] ISPD, 2001, pp:130-135 [Conf] - Robert K. Brayton, Sunil P. Khatri
**Multi-Valued Logic Synthesis.**[Citation Graph (0, 0)][DBLP] VLSI Design, 1999, pp:196-105 [Conf] - Edward Hursey, Nikhil Jayakumar, Sunil P. Khatri
**Non-Manhattan Routing Using a Manhattan Router.**[Citation Graph (0, 0)][DBLP] VLSI Design, 2005, pp:445-450 [Conf] - Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
**Sequential Multi-Valued Network Simplification using Redundancy Removal.**[Citation Graph (0, 0)][DBLP] VLSI Design, 1999, pp:206-211 [Conf] - Amit Narayan, Sunil P. Khatri, Jawahar Jain, Masahiro Fujita, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
**A study of composition schemes for mixed apply/compose based construction of ROBDDs.**[Citation Graph (0, 0)][DBLP] VLSI Design, 1996, pp:249-253 [Conf] - Sabyasachi Das, Sunil P. Khatri
**An efficient and regular routing methodology for datapath designsusing net regularity extraction.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:1, pp:93-101 [Journal] - Sunil P. Khatri, Subarnarekha Sinha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
**SPFD-based wire removal in standard-cell and network-of-PLA circuits.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:7, pp:1020-1030 [Journal] - Nikhil Jayakumar, Sunil P. Khatri
**An algorithm to minimize leakage through simultaneous input vector control and circuit modification.**[Citation Graph (0, 0)][DBLP] DATE, 2007, pp:618-623 [Conf] - Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri
**A Structured ASIC Design Approach Using Pass Transistor Logic.**[Citation Graph (0, 0)][DBLP] ISCAS, 2007, pp:1787-1790 [Conf] - Chunjie Duan, K. Gulat, Sunil P. Khatri
**Memory-based crosstalk canceling CODECs for on-chip buses.**[Citation Graph (0, 0)][DBLP] ISCAS, 2006, pp:- [Conf] - Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri
**A probabilistic method to determine the minimum leakage vector for combinational designs.**[Citation Graph (0, 0)][DBLP] ISCAS, 2006, pp:- [Conf] - Kanupriya Gulati, M. Lovell, Sunil P. Khatri
**Efficient don't care computation for hierarchical designs.**[Citation Graph (0, 0)][DBLP] ISCAS, 2006, pp:- [Conf] - Chunjie Duan, Sunil P. Khatri
**Computing during supply voltage switching in DVS enabled real-time processors.**[Citation Graph (0, 0)][DBLP] ISCAS, 2006, pp:- [Conf] - Rajesh Garg, Sunil P. Khatri
**Generalized buffering of PTL logic stages using Boolean division.**[Citation Graph (0, 0)][DBLP] ISCAS, 2006, pp:- [Conf] - Jeff Cobb, Rajesh Garg, Sunil P. Khatri
**A methodology for interconnect dimension determination.**[Citation Graph (0, 0)][DBLP] ISPD, 2007, pp:189-195 [Conf] - Nikhil Jayakumar, Sunil P. Khatri
**A Predictably Low-Leakage ASIC Design Style.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2007, v:15, n:3, pp:276-285 [Journal] **Efficient analytical determination of the SEU-induced pulse shape.**[Citation Graph (, )][DBLP]**Fast circuit simulation on graphics processing units.**[Citation Graph (, )][DBLP]**Accelerating statistical static timing analysis using graphics processing units.**[Citation Graph (, )][DBLP]**Towards acceleration of fault simulation using graphics processing units.**[Citation Graph (, )][DBLP]**A fast, analytical estimator for the SEU-induced pulse width in combinational designs.**[Citation Graph (, )][DBLP]**Forbidden transition free crosstalk avoidance CODEC design.**[Citation Graph (, )][DBLP]**Clock Distribution Scheme using Coplanar Transmission Lines.**[Citation Graph (, )][DBLP]**A Single-supply True Voltage Level Shifter.**[Citation Graph (, )][DBLP]**Energy Efficient and High Speed On-Chip Ternary Bus.**[Citation Graph (, )][DBLP]**A Delay-efficient Radiation-hard Digital Design Approach Using CWSP Elements.**[Citation Graph (, )][DBLP]**Implementing digital logic with sinusoidal supplies.**[Citation Graph (, )][DBLP]**A SAT-Based Scheme to Determine Optimal Fix-Free Codes.**[Citation Graph (, )][DBLP]**Toggle Equivalence Preserving (TEP) Logic Optimization.**[Citation Graph (, )][DBLP]**Closed-loop modeling of power and temperature profiles of FPGAs.**[Citation Graph (, )][DBLP]**A lithography-friendly structured ASIC design approach.**[Citation Graph (, )][DBLP]**Pipelined network of PLA based circuit design.**[Citation Graph (, )][DBLP]**Improving FPGA routability using network coding.**[Citation Graph (, )][DBLP]**A robust, fast pulsed flip-flop design.**[Citation Graph (, )][DBLP]**Low power and high performance sram design using bank-based selective forward body bias.**[Citation Graph (, )][DBLP]**Robust window-based multi-node technology-independent logic minimization.**[Citation Graph (, )][DBLP]**VLSI implementation of a non-linear feedback shift register for high-speed cryptography applications.**[Citation Graph (, )][DBLP]**Boolean satisfiability on a graphics processor.**[Citation Graph (, )][DBLP]**An Efficient, Scalable Hardware Engine for Boolean SATisfiability.**[Citation Graph (, )][DBLP]**On the Improvement of Statistical Static Timing Analysis.**[Citation Graph (, )][DBLP]**CMOS Comparators for High-Speed and Low-Power Applications.**[Citation Graph (, )][DBLP]**A novel, highly SEU tolerant digital circuit design approach.**[Citation Graph (, )][DBLP]**Performance model for inter-chip communication considering inductive cross-talk and cost.**[Citation Graph (, )][DBLP]**Modeling dynamic stability of SRAMS in the presence of single event upsets (SEUs).**[Citation Graph (, )][DBLP]**Design and implementation of a sub-threshold BFSK transmitter.**[Citation Graph (, )][DBLP]**SEU hardened clock regeneration circuits.**[Citation Graph (, )][DBLP]**A Timing-Driven Synthesis Technique for Arithmetic Product-of-Sum Expressions.**[Citation Graph (, )][DBLP]**An Inversion-Based Synthesis Approach for Area and Power Efficient Arithmetic Sum-of-Products.**[Citation Graph (, )][DBLP]**A Merged Synthesis Technique for Fast Arithmetic Blocks Involving Sum-of-Products and Shifters.**[Citation Graph (, )][DBLP]**Towards brain-inspired computing**[Citation Graph (, )][DBLP]**Instantaneous noise-based logic**[Citation Graph (, )][DBLP]**Computation using Noise-based Logic: Efficient String Verification over a Slow Communication Channel**[Citation Graph (, )][DBLP]**Noise-based deterministic logic and computing: a brief survey**[Citation Graph (, )][DBLP]
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