The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Sunil P. Khatri: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Van R. Culver, Sunil P. Khatri
    A dynamic voltage scaling algorithm for energy reduction in hard real-time systems. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:842-845 [Conf]
  2. Brock J. LaMeres, Kanupriya Gulati, Sunil P. Khatri
    Controlling inductive cross-talk and power in off-chip buses using CODECs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:850-855 [Conf]
  3. Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards, Sunil P. Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa
    VIS: A System for Verification and Synthesis. [Citation Graph (0, 0)][DBLP]
    CAV, 1996, pp:428-432 [Conf]
  4. Rajesh Garg, Nikhil Jayakumar, Sunil P. Khatri, Gwan Choi
    A design approach for radiation-hard digital electronics. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:773-778 [Conf]
  5. Nikhil Jayakumar, Sandeep Dhar, Sunil P. Khatri
    A self-adjusting scheme to determine the optimum RBB by monitoring leakage currents. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:43-46 [Conf]
  6. Nikhil Jayakumar, Rajesh Garg, Bruce Gamache, Sunil P. Khatri
    A PLA based asynchronous micropipelining approach for subthreshold circuit design. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:419-424 [Conf]
  7. Nikhil Jayakumar, Sunil P. Khatri
    A variation tolerant subthreshold design approach. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:716-719 [Conf]
  8. Sunil P. Khatri, Amit Mehrotra, Robert K. Brayton, Ralph H. J. M. Otten, Alberto L. Sangiovanni-Vincentelli
    A Novel VLSI Layout Fabric for Deep Sub-Micron Applications. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:491-496 [Conf]
  9. Sunil P. Khatri, Amit Narayan, Sriram C. Krishnan, Kenneth L. McMillan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Engineering Change in a Non-Deterministic FSM Setting. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:451-456 [Conf]
  10. Nikhil Saluja, Sunil P. Khatri
    A robust algorithm for approximate compatible observability don't care (CODC) computation. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:422-427 [Conf]
  11. Chunjie Duan, Sunil P. Khatri
    Exploiting Crosstalk to Speed up On-Chip Buse. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:778-783 [Conf]
  12. Brock J. LaMeres, Sunil P. Khatri
    Encoding-Based Minimization of Inductive Cross-Talk for Off-Chip Data Transmission. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1318-1323 [Conf]
  13. Brock J. LaMeres, Sunil P. Khatri
    Bus stuttering: an encoding technique to reduce inductive noise in off-chip data transmission. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:522-527 [Conf]
  14. Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards, Sunil P. Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa
    VIS. [Citation Graph (0, 0)][DBLP]
    FMCAD, 1996, pp:248-256 [Conf]
  15. Jawahar Jain, Amit Narayan, C. Coelho, Sunil P. Khatri, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton, Masahiro Fujita
    Decomposition Techniques for Efficient ROBDD Construction. [Citation Graph (0, 0)][DBLP]
    FMCAD, 1996, pp:419-434 [Conf]
  16. Scott J. Campbell, Sunil P. Khatri
    Resource and delay efficient matrix multiplication using newer FPGA devices. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:308-311 [Conf]
  17. Rajesh Garg, Mario Sanchez, Kanupriya Gulati, Nikhil Jayakumar, Anshul Gupta, Sunil P. Khatri
    A design flow to optimize circuit delay by using standard cells and PLAs. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:217-222 [Conf]
  18. Bo Shen, Sunil P. Khatri, Takis Zourntos
    Implementation of MOSFET based capacitors for digital applications. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:180-186 [Conf]
  19. Wilsin Gosti, Sunil P. Khatri, Alberto L. Sangiovanni-Vincentelli
    Addressing the Timing Closure Problem by Integrating Logic Optimization and Placement. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:224-231 [Conf]
  20. Nikhil Jayakumar, Sunil P. Khatri
    A metal and via maskset programmable VLSI design methodology using PLAs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:590-594 [Conf]
  21. A. Kapoor, Nikhil Jayakumar, Sunil P. Khatri
    A novel clock distribution and dynamic de-skewing methodology. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:626-631 [Conf]
  22. Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Cross-Talk Immune VLSI Design Using a Network of PLAs Embedded in a Regular Layout Fabric. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:412-418 [Conf]
  23. Ganesh Venkataraman, Nikhil Jayakumar, Jiang Hu, Peng Li, Sunil P. Khatri, Anand Rajaram, Patrick McGuinness, Charles J. Alpert
    Practical techniques to reduce skew and its variations in buffered clock networks. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:592-596 [Conf]
  24. Nikhil Jayakumar, Sunil P. Khatri, Kanupriya Gulati, Alexander Sprintson
    Network coding for routability improvement in VLSI. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:820-823 [Conf]
  25. Seraj Ahmad, Nikhil Jayakumar, Vijay Balasubramanian, Edward Hursey, Sunil P. Khatri, Rabi N. Mahapatra
    X-Routing using Two Manhattan Route Instances. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:45-52 [Conf]
  26. Nikhil Jayakumar, Sunil P. Khatri
    Minimum Energy Near-threshold Network of PLA based Design. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:399-404 [Conf]
  27. Brock J. LaMeres, Sunil P. Khatri
    Broadband Impedance Matching for Inductive Interconnect in VLSI Packages. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:683-688 [Conf]
  28. Subarnarekha Sinha, Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Binary and Multi-Valued SPFD-Based Wire Removal in PLA Networks. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:494-503 [Conf]
  29. Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri
    An algebraic decision diagram (ADD) based technique to find leakage histograms of combinational designs. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:111-114 [Conf]
  30. Nikhil Jayakumar, Sunil P. Khatri
    An ASIC design methodology with predictably low leakage, using leakage-immune standard cells. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:128-133 [Conf]
  31. Sabyasachi Das, Sunil P. Khatri
    A regularity-driven fast gridless detailed router for high frequency datapath designs. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:130-135 [Conf]
  32. Robert K. Brayton, Sunil P. Khatri
    Multi-Valued Logic Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:196-105 [Conf]
  33. Edward Hursey, Nikhil Jayakumar, Sunil P. Khatri
    Non-Manhattan Routing Using a Manhattan Router. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:445-450 [Conf]
  34. Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Sequential Multi-Valued Network Simplification using Redundancy Removal. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:206-211 [Conf]
  35. Amit Narayan, Sunil P. Khatri, Jawahar Jain, Masahiro Fujita, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    A study of composition schemes for mixed apply/compose based construction of ROBDDs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:249-253 [Conf]
  36. Sabyasachi Das, Sunil P. Khatri
    An efficient and regular routing methodology for datapath designsusing net regularity extraction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:1, pp:93-101 [Journal]
  37. Sunil P. Khatri, Subarnarekha Sinha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    SPFD-based wire removal in standard-cell and network-of-PLA circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:7, pp:1020-1030 [Journal]
  38. Nikhil Jayakumar, Sunil P. Khatri
    An algorithm to minimize leakage through simultaneous input vector control and circuit modification. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:618-623 [Conf]
  39. Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri
    A Structured ASIC Design Approach Using Pass Transistor Logic. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1787-1790 [Conf]
  40. Chunjie Duan, K. Gulat, Sunil P. Khatri
    Memory-based crosstalk canceling CODECs for on-chip buses. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  41. Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri
    A probabilistic method to determine the minimum leakage vector for combinational designs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  42. Kanupriya Gulati, M. Lovell, Sunil P. Khatri
    Efficient don't care computation for hierarchical designs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  43. Chunjie Duan, Sunil P. Khatri
    Computing during supply voltage switching in DVS enabled real-time processors. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  44. Rajesh Garg, Sunil P. Khatri
    Generalized buffering of PTL logic stages using Boolean division. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  45. Jeff Cobb, Rajesh Garg, Sunil P. Khatri
    A methodology for interconnect dimension determination. [Citation Graph (0, 0)][DBLP]
    ISPD, 2007, pp:189-195 [Conf]
  46. Nikhil Jayakumar, Sunil P. Khatri
    A Predictably Low-Leakage ASIC Design Style. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:3, pp:276-285 [Journal]

  47. Efficient analytical determination of the SEU-induced pulse shape. [Citation Graph (, )][DBLP]


  48. Fast circuit simulation on graphics processing units. [Citation Graph (, )][DBLP]


  49. Accelerating statistical static timing analysis using graphics processing units. [Citation Graph (, )][DBLP]


  50. Towards acceleration of fault simulation using graphics processing units. [Citation Graph (, )][DBLP]


  51. A fast, analytical estimator for the SEU-induced pulse width in combinational designs. [Citation Graph (, )][DBLP]


  52. Forbidden transition free crosstalk avoidance CODEC design. [Citation Graph (, )][DBLP]


  53. Clock Distribution Scheme using Coplanar Transmission Lines. [Citation Graph (, )][DBLP]


  54. A Single-supply True Voltage Level Shifter. [Citation Graph (, )][DBLP]


  55. Energy Efficient and High Speed On-Chip Ternary Bus. [Citation Graph (, )][DBLP]


  56. A Delay-efficient Radiation-hard Digital Design Approach Using CWSP Elements. [Citation Graph (, )][DBLP]


  57. Implementing digital logic with sinusoidal supplies. [Citation Graph (, )][DBLP]


  58. A SAT-Based Scheme to Determine Optimal Fix-Free Codes. [Citation Graph (, )][DBLP]


  59. Toggle Equivalence Preserving (TEP) Logic Optimization. [Citation Graph (, )][DBLP]


  60. Closed-loop modeling of power and temperature profiles of FPGAs. [Citation Graph (, )][DBLP]


  61. A lithography-friendly structured ASIC design approach. [Citation Graph (, )][DBLP]


  62. Pipelined network of PLA based circuit design. [Citation Graph (, )][DBLP]


  63. Improving FPGA routability using network coding. [Citation Graph (, )][DBLP]


  64. A robust, fast pulsed flip-flop design. [Citation Graph (, )][DBLP]


  65. Low power and high performance sram design using bank-based selective forward body bias. [Citation Graph (, )][DBLP]


  66. Robust window-based multi-node technology-independent logic minimization. [Citation Graph (, )][DBLP]


  67. VLSI implementation of a non-linear feedback shift register for high-speed cryptography applications. [Citation Graph (, )][DBLP]


  68. Boolean satisfiability on a graphics processor. [Citation Graph (, )][DBLP]


  69. An Efficient, Scalable Hardware Engine for Boolean SATisfiability. [Citation Graph (, )][DBLP]


  70. On the Improvement of Statistical Static Timing Analysis. [Citation Graph (, )][DBLP]


  71. CMOS Comparators for High-Speed and Low-Power Applications. [Citation Graph (, )][DBLP]


  72. A novel, highly SEU tolerant digital circuit design approach. [Citation Graph (, )][DBLP]


  73. Performance model for inter-chip communication considering inductive cross-talk and cost. [Citation Graph (, )][DBLP]


  74. Modeling dynamic stability of SRAMS in the presence of single event upsets (SEUs). [Citation Graph (, )][DBLP]


  75. Design and implementation of a sub-threshold BFSK transmitter. [Citation Graph (, )][DBLP]


  76. SEU hardened clock regeneration circuits. [Citation Graph (, )][DBLP]


  77. A Timing-Driven Synthesis Technique for Arithmetic Product-of-Sum Expressions. [Citation Graph (, )][DBLP]


  78. An Inversion-Based Synthesis Approach for Area and Power Efficient Arithmetic Sum-of-Products. [Citation Graph (, )][DBLP]


  79. A Merged Synthesis Technique for Fast Arithmetic Blocks Involving Sum-of-Products and Shifters. [Citation Graph (, )][DBLP]


  80. Towards brain-inspired computing [Citation Graph (, )][DBLP]


  81. Instantaneous noise-based logic [Citation Graph (, )][DBLP]


  82. Computation using Noise-based Logic: Efficient String Verification over a Slow Communication Channel [Citation Graph (, )][DBLP]


  83. Noise-based deterministic logic and computing: a brief survey [Citation Graph (, )][DBLP]


Search in 0.004secs, Finished in 0.008secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002