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Charles E. Stroud: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. T. Raju Damarla, Wei Su, Gerald T. Michael, Moon J. Chung, Charles E. Stroud
    A built-in self test scheme for VLSI. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  2. Charles E. Stroud, Srinivas M. Garimella, John Sunwoo
    On-Chip BIST-Based Diagnosis of Embedded Programmable Logic Cores in System-on-Chip Devices. [Citation Graph (0, 0)][DBLP]
    Computers and Their Applications, 2005, pp:308-313 [Conf]
  3. Srinivas M. Garimella, Charles E. Stroud
    Built-In Self-Test and Diagnosis of Multiple Embedded Cores in SoCs. [Citation Graph (0, 0)][DBLP]
    ESA, 2005, pp:130-136 [Conf]
  4. Daniel Milton, Sachin Dhingra, Charles E. Stroud
    Embedded Processor Based Built-In Self-Test and Diagnosis of Logic and Memory Resources in FPGAs. [Citation Graph (0, 0)][DBLP]
    ESA, 2006, pp:87-93 [Conf]
  5. Lee Lerner, Charles E. Stroud
    An Architecture for Fail-Silent Operation of FPGAs and Configurable SoCs. [Citation Graph (0, 0)][DBLP]
    ESA, 2006, pp:176-182 [Conf]
  6. Miron Abramovici, Charles E. Stroud, Marty Emmert
    Using embedded FPGAs for SoC yield improvement. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:713-724 [Conf]
  7. Charles E. Stroud
    An Automated BIST Approach for General Sequential Logic Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:3-8 [Conf]
  8. John M. Emmert, Stanley Baumgart, Pankaj Kataria, Andrew M. Taylor, Charles E. Stroud, Miron Abramovici
    On-Line Fault Tolerance for FPGA Interconnect with Roving STARs. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:445-454 [Conf]
  9. Miron Abramovici, John M. Emmert, Charles E. Stroud
    Roving Stars: An Integrated Approach To On-Line Testing, Diagnosis, And Fault Tolerance For Fpgas In Adaptive Computing Systems. [Citation Graph (0, 0)][DBLP]
    Evolvable Hardware, 2001, pp:73-92 [Conf]
  10. John M. Emmert, Charles E. Stroud, Brandon Skaggs, Miron Abramovici
    Dynamic Fault Tolerance in FPGAs via Partial Reconfiguration. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:165-174 [Conf]
  11. Charles E. Stroud, Ping Chen, Srinivasa Konala, Miron Abramovici
    Evaluation of FPGA Resources for Built-In Self-Test of Programmable Logic Blocks. [Citation Graph (0, 0)][DBLP]
    FPGA, 1996, pp:107-113 [Conf]
  12. John M. Emmert, Charles E. Stroud, Jason A. Cheatham, Andrew M. Taylor, Pankaj Kataria, Miron Abramovici
    Performance Penalty for Fault Tolerance in Roving STARs. [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:545-554 [Conf]
  13. Charles E. Stroud, Ahmed E. Barbour
    Parallel Processing and Hardware Acceleration for Synthesis of VLSI Devices from Behavioral Models. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1990, pp:470-473 [Conf]
  14. Miron Abramovici, Charles E. Stroud
    BIST-Based Delay-Fault Testing in FPGAs. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2002, pp:131-134 [Conf]
  15. Miron Abramovici, Charles E. Stroud, Matthew Lashinsky, Jeremy Nall, John M. Emmert
    On-Line BIST and Diagnosis of FPGA Interconnect Using Roving STARs. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2001, pp:27-33 [Conf]
  16. Miron Abramovici, Charles E. Stroud, Brandon Skaggs, John M. Emmert
    Improving On-Line BIST-Based Diagnosis for Roving STARs. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2000, pp:31-39 [Conf]
  17. Dayu Yang, Foster F. Dai, Charles E. Stroud
    Built-in self-test for automatic analog frequency response measurement. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2208-2211 [Conf]
  18. Miron Abramovici, Charles E. Stroud
    DIST-based detection and diagnosis of multiple faults in FPGAs. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:785-794 [Conf]
  19. Miron Abramovici, Charles E. Stroud, Carter Hamilton, Sajitha Wijesuriya, Vinay Verma
    Using roving STARs for on-line testing and diagnosis of FPGAs in fault-tolerant applications. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:973-982 [Conf]
  20. Foster F. Dai, Charles E. Stroud, Dayu Yang, Shuying Qi
    Automatic Linearity (IP3) Test with Built-in Pattern Generator and Analyzer. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:271-280 [Conf]
  21. Charles E. Stroud
    Built-In Self-Test for High-Speed Data-Path Circuitry. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:47-56 [Conf]
  22. Charles E. Stroud
    Distractions in Design for Testability and Built-Is Self-Test. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:1112- [Conf]
  23. Charles E. Stroud, Ahmed E. Barbour
    Design for Testability and Test Generation for Static Redundancy System Level Fault-Tolerant Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:812-818 [Conf]
  24. Charles E. Stroud, M. Ding, S. Seshadri, Ramesh Karri, I. Kim, S. Roy, S. Wu
    A Parameterized VHDL Library for On-Line Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:479-488 [Conf]
  25. Charles E. Stroud, John M. Emmert, John R. Bailey, Khushru S. Chhor, Dragan Nikolic
    Bridging fault extraction from physical design data for manufacturing test development. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:760-769 [Conf]
  26. Charles E. Stroud, Eric Lee, Miron Abramovici
    BIST-Based Diagnostics of FPGA Logic Blocks. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:539-547 [Conf]
  27. Charles E. Stroud, Eric Lee, Srinivasa Konala, Miron Abramovici
    Using ILA Testing for BIST in FPGAs. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:68-75 [Conf]
  28. Charles E. Stroud, Keshia N. Leach, Thomas A. Slaughter
    BIST for Xilinx 4000 and Spartan Series FPGAs: A Case Study. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:1258-1267 [Conf]
  29. Charles E. Stroud, Jeremy Nall, Matthew Lashinsky, Miron Abramovici
    BIST-Based Diagnosis of FPGA Interconnect. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:618-627 [Conf]
  30. Charles E. Stroud, John Sunwoo, Srinivas M. Garimella, Jonathan Harris
    Built-In Self-Test for System-on-Chip: A Case Study. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:837-846 [Conf]
  31. Charles E. Stroud, Sajitha Wijesuriya, Carter Hamilton, Miron Abramovici
    Built-in self-test of FPGA interconnect. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:404-411 [Conf]
  32. Henry Chang, Steve Dollens, Gordon Roberts, Charles E. Stroud, Mani Soma, Jacob A. Abraham
    Analog and Mixed Signal Benchmark Circuit Development: Who Needs Them? [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:415-416 [Conf]
  33. Carter Hamilton, Gretchen Gibson, Sajitha Wijesuriya, Charles E. Stroud
    Enhanced Bist-Based Diagnosis of FPGAs via Boundary Scan Access. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:413-419 [Conf]
  34. Charles E. Stroud, T. Raju Damarla
    Improving the efficiency of error identification via signature analysis. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:244-249 [Conf]
  35. Charles E. Stroud, Srinivasa Konala, Ping Chen, Miron Abramovici
    Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!). [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:387-392 [Conf]
  36. Charles E. Stroud, Joe K. Tannehill Jr.
    Applying Built-In Self-Test to Majority Voting Fault Tolerant Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:303-308 [Conf]
  37. Miron Abramovici, Charles E. Stroud, John M. Emmert
    Online BIST and BIST-based diagnosis of FPGA logic blocks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:12, pp:1284-1294 [Journal]
  38. Foster F. Dai, Charles E. Stroud, Dayu Yang
    Automatic linearity and frequency response tests with built-in pattern generator and analyzer. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:6, pp:561-572 [Journal]
  39. Jie Qin, Charles E. Stroud, Foster F. Dai
    Noise Figure Measurement Using Mixed-Signal BIST. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2180-2183 [Conf]
  40. Charles E. Stroud, Dayu Yang, Foster F. Dai
    Analog frequency response measurement in mixed-signal systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  41. John M. Emmert, Charles E. Stroud, Miron Abramovici
    Online Fault Tolerance for FPGA Logic Blocks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:2, pp:216-226 [Journal]
  42. Charles E. Stroud
    Reliability of majority voting based VLSI fault-tolerant circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:4, pp:516-521 [Journal]
  43. Miron Abramovici, Charles E. Stroud
    BIST-based test and diagnosis of FPGA logic blocks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:1, pp:159-172 [Journal]
  44. Jack Smith, Tian Xia, Charles E. Stroud
    An Automated BIST Architecture for Testing and Diagnosing FPGA Interconnect Faults. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2006, v:22, n:3, pp:239-253 [Journal]

  45. Single Event Upset Detection and Correction in Virtex-4 and Virtex-5 FPGAs. [Citation Graph (, )][DBLP]


  46. Built-in Self-Test for Memory Resources in Virtex-4 Field Programmable Gate Arrays. [Citation Graph (, )][DBLP]


  47. Built-In Self-Test of Embedded SEU Detection Cores in Virtex-4 and Virtex-5 FPGAs. [Citation Graph (, )][DBLP]


  48. Embedded Processor Based Fault Injection and SEU Emulation for FPGAs. [Citation Graph (, )][DBLP]


  49. Application of Embedded Systems in Low Earth Orbit for Measurement of Ionospheric Anomalies. [Citation Graph (, )][DBLP]


  50. Automated Generation of Built-In Self-Test and Measurement Circuitry for Mixed-Signal Circuits and Systems. [Citation Graph (, )][DBLP]


  51. Soft Core Embedded Processor Based Built-In Self-Test of FPGAs. [Citation Graph (, )][DBLP]


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