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Publications of Author

1. Batsayan Das, Dipankar Sarkar, Santanu Chattopadhyay
   Model checking on state transition diagram. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2004, pp:412-417 [Conf]
   
2. S. Biswas, P. Srikanth, R. Jha, S. Mukhopadhyay, A. Patra, D. Sarkar
   On-Line Testing of Digital Circuits for n-Detect and Bridging Fault Models. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 2005, pp:88-93 [Conf]
   
3. S. Biswas, S. Mukhopadhyay, P. Patra, D. Sarkar
   Concurrent Testing of Digital Circuits for Advanced Fault Models. [Citation Graph (0, 0)][DBLP]
   DDECS, 2006, pp:204-209 [Conf]
   
4. Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal, Chris Reade
   Hand-in-hand verification of high-level synthesis. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2007, pp:429-434 [Conf]
   
5. Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, S. R. Pentakota, Chris Reade
   A Formal Verification Method of Scheduling in High-level Synthesis. [Citation Graph (0, 0)][DBLP]
   ISQED, 2006, pp:71-78 [Conf]
   
6. Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, S. R. Pentakota, Chris Reade
   Verification of Scheduling in High-level Synthesis. [Citation Graph (0, 0)][DBLP]
   ISVLSI, 2006, pp:141-146 [Conf]
   
7. Dipankar Sarkar
   Status Condition Analysis during Data Path Verification of Sequential Circuits. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2000, pp:70-75 [Conf]
   
8. Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, Chris Reade
   Register Sharing Verification During Data-Path Synthesis. [Citation Graph (0, 0)][DBLP]
   ICCTA, 2007, pp:135-140 [Conf]
   
9. Prodip Bhowal, Dipankar Sarkar, Siddhartha Mukhopadhyay, Anupam Basu
   Fault diagnosis in discrete time hybrid systems - A case study. [Citation Graph (0, 0)][DBLP]
   Inf. Sci., 2007, v:177, n:5, pp:1290-1308 [Journal]