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Santanu Chattopadhyay: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Batsayan Das, Dipankar Sarkar, Santanu Chattopadhyay
    Model checking on state transition diagram. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:412-417 [Conf]
  2. Santanu Chattopadhyay
    Efficient Circuit Specific Pseudoexhaustive Testing with Cellular Automata. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:188-193 [Conf]
  3. Shantanu Gupta, Tarang Vaish, Santanu Chattopadhyay
    Flip-flop chaining architecture for power-efficient scan during test application. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:410-413 [Conf]
  4. Kolin Paul, A. Roy, Prasanta Kumar Nandi, B. N. Roy, M. Deb Purkayastha, Santanu Chattopadhyay, Parimal Pal Chaudhuri
    Theory and Application of Multiple Attractor Cellular Automata for Fault Diagnosis. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:388-0 [Conf]
  5. Debabrata Bagchi, Dipanwita Roy Chowdhury, Joy Mukherjee, Santanu Chattopadhyay
    A Novel Strategy to Test Core Based Designs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:122-127 [Conf]
  6. Santanu Chattopadhyay, Naveen Choudhary
    Genetic Algorithm based Approach for Low Power Combinational Circuit Testing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:552-0 [Conf]
  7. Santanu Chattopadhyay, Parimal Pal Chaudhuri
    Parallel Decoder for Cellular Automata Based Byte Error Correcting Code. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:527-528 [Conf]
  8. Santanu Chattopadhyay, Parimal Pal Chaudhuri
    Genetic Algorithm Based Approach for Integrated State Assignment and Flipflop Selection in Finite State Machine Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:522-527 [Conf]
  9. Santanu Chattopadhyay, Parimal Pal Chaudhuri
    Efficient Signatures with Linear Space Complexity for Detecting Boolean Function Equivalence. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:564-0 [Conf]
  10. Santanu Chattopadhyay, Dipanwita Roy Chowdhury, Subarna Bhattacharjee, Parimal Pal Chaudhuri
    Board level fault diagnosis using cellular automata array. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:343-348 [Conf]
  11. Santanu Chattopadhyay, Manas Kumar Dewangan
    A Combinational Logic Mapper for Actel's SX/AX Family. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:669-672 [Conf]
  12. Santanu Chattopadhyay, S. Mitra, Parimal Pal Chaudhuri
    Cellular automata based architecture of a database query processor. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:320-321 [Conf]
  13. Santanu Chattopadhyay, K. Sudarsana Reddy
    Genetic Algorithm based Test Scheduling and Test Access Mechanism Design for System-on-Chips. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:341-346 [Conf]
  14. Santanu Chattopadhyay, Samir Roy, Parimal Pal Chaudhuri
    Technology mapping on a multi-output logic module built around Cellular Automata Array for a new FPGA architecture. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:57-62 [Conf]
  15. Prabir Dasgupta, Santanu Chattopadhyay, Indranil Sengupta
    An ASIC for Cellular Automata Based Message Authentication. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:538-0 [Conf]
  16. Prabir Dasgupta, Santanu Chattopadhyay, Indranil Sengupta
    Cellular Automata Based Deterministic Test Sequence Generator for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:544-549 [Conf]
  17. S. Nandi, Santanu Chattopadhyay, Parimal Pal Chaudhuri
    Programmable cellular automata based testbed for fault diagnosis in VLSI circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:61-64 [Conf]
  18. Rohit Pandey, Santanu Chattopadhyay
    Low Power Technology Mapping for LUT based FPGA "A Genetic Algorithm Approach". [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:79-84 [Conf]
  19. D. Satyanarayana, Santanu Chattopadhyay, Jakki Sasidhar
    Low Power Combinational Circuit Synthesis targeting Multiplexer based FPGAs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:79-84 [Conf]
  20. Chandan Giri, Dilip Kumar Reddy Tipparthi, Santanu Chattopadhyay
    Genetic Algorithm Based Approach for Hierarchical SOC Test Scheduling. [Citation Graph (0, 0)][DBLP]
    ICCTA, 2007, pp:141-145 [Conf]
  21. Chandan Giri, B. Mallikarjuna Rao, Santanu Chattopadhyay
    Test Data Compression by Spilt-VIHC (SVIHC). [Citation Graph (0, 0)][DBLP]
    ICCTA, 2007, pp:146-150 [Conf]
  22. Santanu Chattopadhyay
    Area Conscious State Assignment with Flip-Flop and Output Polarity Selection for Finite State Machine Synthesis?A Genetic Algorithm Approach. [Citation Graph (0, 0)][DBLP]
    Comput. J., 2005, v:48, n:4, pp:443-450 [Journal]
  23. Santanu Chattopadhyay, Dipanwita Roy Chowdhury, Subarna Bhattacharjee, Parimal Pal Chaudhuri
    Cellular-Automata-Array-Based Diagnosis of Board Level Faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:8, pp:817-828 [Journal]
  24. Santanu Chattopadhyay, Samir Roy, Parimal Pal Chaudhuri
    Synthesis of Highly Testable Fixed-Polarity AND-XOR Canonical Networks-A Genetic Algorithm-Based Approach. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:4, pp:487-490 [Journal]
  25. Prabir Dasgupta, Santanu Chattopadhyay, Parimal Pal Chaudhuri, Indranil Sengupta
    Cellular Automata-Based Recursive Pseudoexhaustive Test Pattern Generator. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:2, pp:177-185 [Journal]
  26. Koppolu Sasidhar, Santanu Chattopadhyay, Parimal Pal Chaudhuri
    CAA Decoder for Cellular Automata Based Byte Error Correcting Code. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:9, pp:1003-1016 [Journal]
  27. Santanu Chattopadhyay, Samir Roy, Parimal Pal Chaudhuri
    KGPMIN: an efficient multilevel multioutput AND-OR-XOR minimizer. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:3, pp:257-265 [Journal]
  28. Chandan Giri, Soumojit Sarkar, Santanu Chattopadhyay
    Test Scheduling for Core-Based SOCs Using Genetic Algorithm Based Heuristic Approach. [Citation Graph (0, 0)][DBLP]
    ICIC (2), 2007, pp:1032-1041 [Conf]
  29. Chandan Giri, Santanu Chattopadhyay
    Reducing Test-bus Power Consumption in Huffman Coding Based Test Data Compression for SOCs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3679-3682 [Conf]

  30. Test Pattern Selection and Customization Targeting Reduced Dynamic and Leakage Power Consumption. [Citation Graph (, )][DBLP]


  31. Mesh-of-tree deterministic routing for network-on-chip architecture. [Citation Graph (, )][DBLP]


  32. Don't care filling for power minimization in VLSI circuit testing. [Citation Graph (, )][DBLP]


  33. An efficient greedy approach to PLA folding. [Citation Graph (, )][DBLP]


  34. An efficient finite precision realization of the block adaptive decision feedback equalizer. [Citation Graph (, )][DBLP]


  35. Customizing pattern set for test power reduction via improved X-identification and reordering. [Citation Graph (, )][DBLP]


  36. Integrated Power-Gating and State Assignment for Low Power FSM Synthesis. [Citation Graph (, )][DBLP]


  37. A genetic algorithm based heuristic technique for power constrained test scheduling in core-based SOCs. [Citation Graph (, )][DBLP]


  38. Synthesis & Testing for Low Power. [Citation Graph (, )][DBLP]


  39. Synthesis of Finite State Machines for Low Power and Testability. [Citation Graph (, )][DBLP]


  40. Circuit Partitioning Using Particle Swarm Optimization for Pseudo-Exhaustive Testing. [Citation Graph (, )][DBLP]


  41. A Comparative Performance Evaluation of Network-on-Chip Architectures under Self-Similar Traffic. [Citation Graph (, )][DBLP]


  42. Efficient Don't Care Filling for Power Reduction during Testing. [Citation Graph (, )][DBLP]


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