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Swarup Bhunia: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Animesh Datta, Swarup Bhunia, Jung Hwan Choi, Saibal Mukhopadhyay, Kaushik Roy
    Speed binning aware design methodology to improve profit under parameter variations. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:712-717 [Conf]
  2. Ashish Goel, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy
    Low-overhead design of soft-error-tolerant scan flip-flops with enhanced-scan capability. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:665-670 [Conf]
  3. Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy
    A Statistical Approach to Area-Constrained Yield Enhancement for Pipelined Circuits under Parameter Variations. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:170-175 [Conf]
  4. Swarup Bhunia, Hai Li, Kaushik Roy
    A High Performance IDDQ Testable Cache for Scaled CMOS Technologies. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:157-0 [Conf]
  5. Swaroop Ghosh, Swarup Bhunia, Kaushik Roy
    Shannon Expansion Based Supply-Gated Logic for Improved Power and Testability. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:404-409 [Conf]
  6. Swarup Bhunia, Nilanjan Banerjee, Qikai Chen, Hamid Mahmoodi-Meimand, Kaushik Roy
    A novel synthesis approach for active leakage power reduction using dynamic supply gating. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:479-484 [Conf]
  7. Swarup Bhunia, Kaushik Roy, Jaume Segura
    A novel wavelet transform based transient current analysis for fault detection and localization. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:361-366 [Conf]
  8. Nilanjan Banerjee, Kaushik Roy, Hamid Mahmoodi-Meimand, Swarup Bhunia
    Low power synthesis of dynamic logic circuits using fine-grained clock gating. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:862-867 [Conf]
  9. Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy
    A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1136-1141 [Conf]
  10. Swarup Bhunia, Kaushik Roy
    Fault Detection and Diagnosis Using Wavelet Based Transient Current Analysis. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1118- [Conf]
  11. Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy
    Trim Bit Setting of Analog Filters Using Wavelet-Based Supply Current Analysis. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:704-705 [Conf]
  12. Lih-Yih Chiou, Swarup Bhunia, Kaushik Roy
    Synthesis of Application-Specific Highly-Efficient Multi-Mode Systems for Low-Power Applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10096-10103 [Conf]
  13. Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Nilanjan Banerjee, Kaushik Roy
    Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:926-931 [Conf]
  14. Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy
    Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:224-229 [Conf]
  15. Arijit Raychowdhury, Bipul Chandra Paul, Swarup Bhunia, Kaushik Roy
    Ultralow power computing with sub-threshold leakage: a comparative study of bulk and SOI technologies. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:856-861 [Conf]
  16. Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy
    First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique. [Citation Graph (0, 0)][DBLP]
    DFT, 2004, pp:314-315 [Conf]
  17. Debjyoti Ghosh, Swarup Bhunia, Kaushik Roy
    Multiple Scan Chain Design Technique for Power Reduction during Test Application in BIST. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:191-198 [Conf]
  18. Hai Li, Swarup Bhunia, Yiran Chen, T. N. Vijaykumar, Kaushik Roy
    Deterministic Clock Gating for Microprocessor Power Reduction. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:113-0 [Conf]
  19. Swaroop Ghosh, Swarup Bhunia, Kaushik Roy
    A new paradigm for low-power, variation-tolerant circuit synthesis using critical path isolation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:619-624 [Conf]
  20. Nilanjan Banerjee, Arijit Raychowdhury, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy
    Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:206-214 [Conf]
  21. Swarup Bhunia, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Debjyoti Ghosh, Kaushik Roy
    A Novel Low-Power Scan Design Technique Using Supply Gating. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:60-65 [Conf]
  22. Arijit Bishnu, Swarup Bhunia, C. A. Murthy, Bhargab B. Bhattacharya, Malay Kumar Kundu, Tinku Acharya
    Content based image retrieval: related issues using Euler vector. [Citation Graph (0, 0)][DBLP]
    ICIP (2), 2002, pp:585-588 [Conf]
  23. Debjyoti Ghosh, Swarup Bhunia, Kaushik Roy
    A Technique to Reduce Power and Test Application Time in BIST. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:182-183 [Conf]
  24. Animesh Datta, Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy
    Yield Prediction of High Performance Pipelined Circuit with Respect to Delay Failures in Sub-100nm Technology. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:275-280 [Conf]
  25. Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy
    Delay Fault Localization in Test-Per-Scan BIST Using Built-In Delay Sensor. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2006, pp:31-36 [Conf]
  26. Amit Agarwal, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher, Kaushik Roy
    Effectiveness of low power dual-Vt designs in nano-scale technologies under process parameter variations. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:14-19 [Conf]
  27. Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy
    Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:389-394 [Conf]
  28. Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Kaushik Roy
    Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Partitioning. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:453-458 [Conf]
  29. Animesh Datta, Swarup Bhunia, Nilanjan Banerjee, Kaushik Roy
    A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:358-363 [Conf]
  30. Sivasubramaniam Krishnamurthy, Somnath Paul, Swarup Bhunia
    Adaptation to Temperature-Induced Delay Variations in Logic Circuits Using Low-Overhead Online Delay Calibration. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:755-760 [Conf]
  31. Swarup Bhunia, Soumya K. Ghosh, Pramod Kumar, Partha Pratim Das, Jayanta Mukherjee
    Design, Simulation and Synthesis of an ASIC for Fractal Image Compression. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:544-547 [Conf]
  32. Swarup Bhunia, Subhashis Majumder, Ayan Sircar, Susmita Sur-Kolay, Bhargab B. Bhattacharya
    Topological Routing Amidst Polygonal Obstacles. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:274-279 [Conf]
  33. Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy
    Process Variations and Process-Tolerant Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:699-704 [Conf]
  34. Swarup Bhunia, Kaushik Roy
    Dynamic Supply Current Testing of Analog Circuits Using Wavelet Transform. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:302-310 [Conf]
  35. Qikai Chen, Hamid Mahmoodi-Meimand, Swarup Bhunia, Kaushik Roy
    Modeling and Testing of SRAM for New Failure Mechanisms Due to Process Variations in Nanoscale CMOS. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:292-297 [Conf]
  36. Somnath Paul, Rajat Subhra Chakraborty, Swarup Bhunia
    VIm-Scan: A Low Overhead Scan Design Approach for Protection of Secret Key in Scan-Based Secure Chips. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:455-460 [Conf]
  37. Swarup Bhunia, Animesh Datta, Nilanjan Banerjee, Kaushik Roy
    GAARP: A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:6, pp:752-766 [Journal]
  38. Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy
    Delay Modeling and Statistical Design of Pipelined Circuit Under Process Variation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2427-2436 [Journal]
  39. Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy
    Modeling and analysis of loading effect on leakage of nanoscaled bulk-CMOS logic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:8, pp:1486-1495 [Journal]
  40. Lih-Yih Chiou, Swarup Bhunia, Kaushik Roy
    Synthesis of application-specific highly efficient multi-mode cores for embedded systems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2005, v:4, n:1, pp:168-188 [Journal]
  41. Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Saibal Mukhopadhyay, Kaushik Roy
    Low-power scan design using first-level supply gating. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:3, pp:384-395 [Journal]
  42. Swarup Bhunia, Kaushik Roy
    A novel wavelet transform-based transient current analysis for fault detection and localization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:4, pp:503-507 [Journal]
  43. Qikai Chen, Hamid Mahmoodi-Meimand, Swarup Bhunia, Kaushik Roy
    Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:11, pp:1286-1295 [Journal]
  44. Arijit Raychowdhury, Bipul Chandra Paul, Swarup Bhunia, Kaushik Roy
    Computing with subthreshold leakage: device/circuit/architecture co-design for ultralow-power subthreshold operation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:11, pp:1213-1224 [Journal]
  45. Hai Li, Swarup Bhunia, Yiran Chen, Kaushik Roy, T. N. Vijaykumar
    DCG: deterministic clock-gating for low-power microprocessor design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:3, pp:245-254 [Journal]
  46. Nilanjan Banerjee, Arijit Raychowdhury, Kaushik Roy, Swarup Bhunia, Hamid Mahmoodi
    Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:9, pp:1034-1039 [Journal]
  47. Swaroop Ghosh, Swarup Bhunia, Kaushik Roy
    Low-overhead circuit synthesis for temperature adaptation using dynamic voltage scheduling. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1532-1537 [Conf]
  48. Swaroop Ghosh, Patrick Ndai, Swarup Bhunia, Kaushik Roy
    Tolerance to Small Delay Defects by Adaptive Clock Stretching. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2007, pp:244-252 [Conf]
  49. Somnath Paul, Rajat Subhra Chakraborty, Swarup Bhunia
    Defect-Aware Configurable Computing in Nanoscale Crossbar for Improved Yield. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2007, pp:29-36 [Conf]
  50. Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Nilanjan Banerjee, Kaushik Roy
    Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  51. Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy
    Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  52. Swaroop Ghosh, Swarup Bhunia, Kaushik Roy
    Low-Power and testable circuit synthesis using Shannon decomposition. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:4, pp:- [Journal]
  53. Amit Agarwal, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher, Kaushik Roy
    Device-Aware Yield-Centric Dual-Vt Design Under Parameter Variations in Nanoscale Technologies. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:6, pp:660-671 [Journal]
  54. Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy
    Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:3, pp:243-255 [Journal]
  55. Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy
    Defect Oriented Testing of Analog Circuits Using Wavelet Analysis of Dynamic Supply Current. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:2, pp:147-159 [Journal]

  56. Ultralow-Power Reconfigurable Computing with Complementary Nano-Electromechanical Carbon Nanotube Switches. [Citation Graph (, )][DBLP]


  57. MBARC: A scalable memory based reconfigurable computing framework for nanoscale devices. [Citation Graph (, )][DBLP]


  58. MERO: A Statistical Approach for Hardware Trojan Detection. [Citation Graph (, )][DBLP]


  59. Self-referencing: A Scalable Side-Channel Approach for Hardware Trojan Detection. [Citation Graph (, )][DBLP]


  60. Reconfigurable computing using content addressable memory for improved performance and resource usage. [Citation Graph (, )][DBLP]


  61. Collective computing based on swarm intelligence. [Citation Graph (, )][DBLP]


  62. Fine-Grained Supply Gating Through Hypergraph Partitioning and Shannon Decomposition for Active Power Reduction. [Citation Graph (, )][DBLP]


  63. Harvesting Wasted Heat in a Microprocessor Using Thermoelectric Generators: Modeling, Analysis and Measurement. [Citation Graph (, )][DBLP]


  64. Towards Trojan-Free Trusted ICs: Problem Analysis and Detection Scheme. [Citation Graph (, )][DBLP]


  65. On-die CMOS voltage droop detection and dynamiccompensation. [Citation Graph (, )][DBLP]


  66. Low-overhead design technique for calibration of maximum frequency at multiple operating points. [Citation Graph (, )][DBLP]


  67. Hybrid CMOS-STTRAM non-volatile FPGA: design challenges and optimization approaches. [Citation Graph (, )][DBLP]


  68. Hardware protection and authentication through netlist level obfuscation. [Citation Graph (, )][DBLP]


  69. Security against hardware Trojan through a novel application of design obfuscation. [Citation Graph (, )][DBLP]


  70. A variation-aware preferential design approach for memory based reconfigurable computing. [Citation Graph (, )][DBLP]


  71. A circuit-software co-design approach for improving EDP in reconfigurable frameworks. [Citation Graph (, )][DBLP]


  72. Memory based computation using embedded cache for processor yield and reliability improvement. [Citation Graph (, )][DBLP]


  73. Low power FPGA design using hybrid CMOS-NEMS approach. [Citation Graph (, )][DBLP]


  74. Low power design under parameter variations. [Citation Graph (, )][DBLP]


  75. VAIL: variation-aware issue logic and performance binning for processor yield and profit improvement. [Citation Graph (, )][DBLP]


  76. Towards Uniform Temperature Distribution in SOI Circuits Using Carbon Nanotube Based Thermal Interconnect. [Citation Graph (, )][DBLP]


  77. Micropipeline-Based Asynchronous Design Methodology for Robust System Design Using Nanoscale Crossbar. [Citation Graph (, )][DBLP]


  78. Analysis and Robust Design of Diode-Resistor Based Nanoscale Crossbar PLA Circuits. [Citation Graph (, )][DBLP]


  79. RTL Hardware IP Protection Using Key-Based Control and Data Flow Obfuscation. [Citation Graph (, )][DBLP]


  80. On-Demand Transparency for Improving Hardware Trojan Detectability. [Citation Graph (, )][DBLP]


  81. Dynamic Evaluation of Hardware Trust. [Citation Graph (, )][DBLP]


  82. Security Through Obscurity: An Approach for Protecting Register Transfer Level Hardware IP. [Citation Graph (, )][DBLP]


  83. Low power design under parameter variations. [Citation Graph (, )][DBLP]


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