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Saibal Mukhopadhyay: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Animesh Datta, Swarup Bhunia, Jung Hwan Choi, Saibal Mukhopadhyay, Kaushik Roy
    Speed binning aware design methodology to improve profit under parameter variations. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:712-717 [Conf]
  2. Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy
    A Statistical Approach to Area-Constrained Yield Enhancement for Pipelined Circuits under Parameter Variations. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:170-175 [Conf]
  3. Saibal Mukhopadhyay, Arijit Raychowdhury, Hamid Mahmoodi-Meimand, Kaushik Roy
    Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:176-181 [Conf]
  4. Amit Agarwal, Chris H. Kim, Saibal Mukhopadhyay, Kaushik Roy
    Leakage in nano-scale technologies: mechanisms, impact and design considerations. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:6-11 [Conf]
  5. Swaroop Ghosh, Saibal Mukhopadhyay, Kee-Jong Kim, Kaushik Roy
    Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:971-976 [Conf]
  6. Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy
    Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:169-174 [Conf]
  7. Qikai Chen, Saibal Mukhopadhyay, Aditya Bansal, Kaushik Roy
    Circuit-aware device design methodology for nanometer technologies: a case study for low power SRAM design. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:983-988 [Conf]
  8. Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Nilanjan Banerjee, Kaushik Roy
    Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:926-931 [Conf]
  9. Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy
    Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:224-229 [Conf]
  10. Saibal Mukhopadhyay, Qikai Chen, Kaushik Roy
    Memories in Scaled Technologies: A Review of Process Induced Failures, Test Methodologies, and Fault Tolerance. [Citation Graph (0, 0)][DBLP]
    DDECS, 2007, pp:69-74 [Conf]
  11. Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy
    Statistical design and optimization of SRAM cell for yield enhancement. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:10-13 [Conf]
  12. Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy
    Modeling of Ballistic Carbon Nanotube Field Effect Transistors for Efficient Circuit Simulation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:487-490 [Conf]
  13. Kaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici
    Double-gate SOI devices for low-power and high-performance applications. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:217-224 [Conf]
  14. Swarup Bhunia, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Debjyoti Ghosh, Kaushik Roy
    A Novel Low-Power Scan Design Technique Using Supply Gating. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:60-65 [Conf]
  15. Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy
    A Feasibility Study of Subthreshold SRAM Across Technology Generations. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:417-424 [Conf]
  16. Qikai Chen, Saibal Mukhopadhyay, Hamid Mahmoodi, Kaushik Roy
    Process Variation Tolerant Online Current Monitor for Robust Systems. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:171-176 [Conf]
  17. Animesh Datta, Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy
    Yield Prediction of High Performance Pipelined Circuit with Respect to Delay Failures in Sub-100nm Technology. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:275-280 [Conf]
  18. Chris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, Kaushik Roy
    A forward body-biased low-leakage SRAM cache: device and architecture considerations. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:6-9 [Conf]
  19. Saibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang, Kaushik Roy
    Modeling and analysis of total leakage currents in nanoscale double gate devices and circuits. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:8-13 [Conf]
  20. Saibal Mukhopadhyay, Kaushik Roy
    Modeling and estimation of total leakage current in nano-scaled CMOS devices considering the effect of parameter variation. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:172-175 [Conf]
  21. Saibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy
    Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:410-415 [Conf]
  22. Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy
    Design of High Performance Sense Amplifier Using Independent Gate Control in sub-50nm Double-Gate MOSFET. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:490-495 [Conf]
  23. Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy
    Modeling and Estimation of Leakage in Sub-90nm Devices. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:65-0 [Conf]
  24. Kaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici
    Double-Gate SOI Devices for Low-Power and High-Performance Applications. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:445-452 [Conf]
  25. Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy
    Process Variations and Process-Tolerant Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:699-704 [Conf]
  26. Kaushik Roy, Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand
    Leakage Current in Deep-Submicron CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2002, v:11, n:6, pp:575-600 [Journal]
  27. Amit Agarwal, Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy, Chris H. Kim
    Leakage Power Analysis and Reduction for Nanoscale Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2006, v:26, n:2, pp:68-80 [Journal]
  28. Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy
    Delay Modeling and Statistical Design of Pipelined Circuit Under Process Variation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2427-2436 [Journal]
  29. Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy
    Modeling and analysis of loading effect on leakage of nanoscaled bulk-CMOS logic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:8, pp:1486-1495 [Journal]
  30. Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy
    Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:12, pp:1859-1880 [Journal]
  31. Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy
    Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits based on device geometry and doping profile. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:3, pp:363-381 [Journal]
  32. Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy
    A circuit-compatible model of ballistic carbon nanotube field-effect transistors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:10, pp:1411-1420 [Journal]
  33. Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Saibal Mukhopadhyay, Kaushik Roy
    Low-power scan design using first-level supply gating. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:3, pp:384-395 [Journal]
  34. Chris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, Kaushik Roy
    A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:3, pp:349-357 [Journal]
  35. Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy
    A novel high-performance and robust sense amplifier using independent gate control in sub-50-nm double-gate MOSFET. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:2, pp:183-192 [Journal]
  36. Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Nilanjan Banerjee, Kaushik Roy
    Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  37. Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy
    Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  38. Saibal Mukhopadhyay, Cassondra Neau, R. T. Cakici, Amit Agarwal, Chris H. Kim, Kaushik Roy
    Gate leakage reduction for scaled devices using transistor stacking. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:4, pp:716-730 [Journal]

  39. Accuracy-aware SRAM: a reconfigurable low power SRAM architecture for mobile multimedia applications. [Citation Graph (, )][DBLP]


  40. Hybrid CMOS-STTRAM non-volatile FPGA: design challenges and optimization approaches. [Citation Graph (, )][DBLP]


  41. Yield estimation of SRAM circuits using "Virtual SRAM Fab". [Citation Graph (, )][DBLP]


  42. A variation-aware preferential design approach for memory based reconfigurable computing. [Citation Graph (, )][DBLP]


  43. A methodology for robust, energy efficient design of Spin-Torque-Transfer RAM arrays at scaled technologies. [Citation Graph (, )][DBLP]


  44. A circuit-software co-design approach for improving EDP in reconfigurable frameworks. [Citation Graph (, )][DBLP]


  45. Pre-Si estimation and compensation of SRAM layout deficiencies to achieve target performance and yield. [Citation Graph (, )][DBLP]


  46. Capacitive coupling based transient negative bit-line voltage (Tran-NBL) scheme for improving write-ability of SRAM design in nanometer technologies. [Citation Graph (, )][DBLP]


  47. Design and analysis of Thin-BOX FD/SOI devices for low-power and stable SRAM in sub-50nm technologies. [Citation Graph (, )][DBLP]


  48. Experimental analysis of sequence dependence on energy saving for error tolerant image processing. [Citation Graph (, )][DBLP]


  49. Slew-aware clock tree design for reliable subthreshold circuits. [Citation Graph (, )][DBLP]


  50. Analysis of thermal behaviors of spin-torque-transfer RAM: a simulation study. [Citation Graph (, )][DBLP]


  51. An energy efficient cache design using spin torque transfer (STT) RAM. [Citation Graph (, )][DBLP]


  52. Variability Analysis for sub-100nm PD/SOI Sense-Amplifier. [Citation Graph (, )][DBLP]


  53. Accurate buffer modeling with slew propagation in subthreshold circuits. [Citation Graph (, )][DBLP]


  54. A low power system with adaptive data compression for wireless monitoring of physiological signals and its application to wireless electroencephalography. [Citation Graph (, )][DBLP]


  55. Signal processing methods and hardware-structure for on-line characterization of thermal gradients in many-core processors. [Citation Graph (, )][DBLP]


  56. Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs. [Citation Graph (, )][DBLP]


  57. Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies. [Citation Graph (, )][DBLP]


  58. Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry. [Citation Graph (, )][DBLP]


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