Saibal Mukhopadhyay, Kaushik Roy Modeling and estimation of total leakage current in nano-scaled CMOS devices considering the effect of parameter variation. [Citation Graph (0, 0)][DBLP] ISLPED, 2003, pp:172-175 [Conf]
Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits based on device geometry and doping profile. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:3, pp:363-381 [Journal]
Yield estimation of SRAM circuits using "Virtual SRAM Fab". [Citation Graph (, )][DBLP]
A variation-aware preferential design approach for memory based reconfigurable computing. [Citation Graph (, )][DBLP]
A methodology for robust, energy efficient design of Spin-Torque-Transfer RAM arrays at scaled technologies. [Citation Graph (, )][DBLP]
A circuit-software co-design approach for improving EDP in reconfigurable frameworks. [Citation Graph (, )][DBLP]
Pre-Si estimation and compensation of SRAM layout deficiencies to achieve target performance and yield. [Citation Graph (, )][DBLP]
Capacitive coupling based transient negative bit-line voltage (Tran-NBL) scheme for improving write-ability of SRAM design in nanometer technologies. [Citation Graph (, )][DBLP]
Design and analysis of Thin-BOX FD/SOI devices for low-power and stable SRAM in sub-50nm technologies. [Citation Graph (, )][DBLP]
Experimental analysis of sequence dependence on energy saving for error tolerant image processing. [Citation Graph (, )][DBLP]
Slew-aware clock tree design for reliable subthreshold circuits. [Citation Graph (, )][DBLP]
Analysis of thermal behaviors of spin-torque-transfer RAM: a simulation study. [Citation Graph (, )][DBLP]
An energy efficient cache design using spin torque transfer (STT) RAM. [Citation Graph (, )][DBLP]
Variability Analysis for sub-100nm PD/SOI Sense-Amplifier. [Citation Graph (, )][DBLP]
Accurate buffer modeling with slew propagation in subthreshold circuits. [Citation Graph (, )][DBLP]
A low power system with adaptive data compression for wireless monitoring of physiological signals and its application to wireless electroencephalography. [Citation Graph (, )][DBLP]
Signal processing methods and hardware-structure for on-line characterization of thermal gradients in many-core processors. [Citation Graph (, )][DBLP]
Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs. [Citation Graph (, )][DBLP]
Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies. [Citation Graph (, )][DBLP]
Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry. [Citation Graph (, )][DBLP]
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