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Azadeh Davoodi: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Azadeh Davoodi, Ankur Srivastava
    Simultaneous floorplanning and resource binding: a probabilistic approach. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:517-522 [Conf]
  2. Azadeh Davoodi, Ankur Srivastava
    Wake-up protocols for controlling current surges in MTCMOS-based technology. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:868-871 [Conf]
  3. Azadeh Davoodi, Ankur Srivastava
    Variability driven gate sizing for binning yield optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:959-964 [Conf]
  4. Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava
    High level techniques for power-grid noise immunity. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:13-18 [Conf]
  5. Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava
    Variability inspired implementation selection problem. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:423-427 [Conf]
  6. Vishal Khandelwal, Azadeh Davoodi, Akash Nanavati, Ankur Srivastava
    A Probabilistic Approach to Buffer Insertion. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:560-567 [Conf]
  7. Vishal Khandelwal, Azadeh Davoodi, Ankur Srivastava
    Efficient statistical timing analysis through error budgeting. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:473-477 [Conf]
  8. Jennifer L. Wong, Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava, Miodrag Potkonjak
    Wire-length prediction using statistical techniques. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:702-705 [Conf]
  9. Azadeh Davoodi, Ankur Srivastava
    Variability-Driven Buffer Insertion Considering Correlations. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:425-430 [Conf]
  10. Azadeh Davoodi, Ankur Srivastava
    Effective graph theoretic techniques for the generalized low power binding problem. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:152-157 [Conf]
  11. Azadeh Davoodi, Ankur Srivastava
    Voltage scheduling under unpredictabilities: a risk management paradigm. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:302-305 [Conf]
  12. Azadeh Davoodi, Ankur Srivastava
    Probabilistic dual-Vth leakage optimization under variability. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:143-148 [Conf]
  13. Azadeh Davoodi, Ankur Srivastava
    Probabilistic evaluation of solutions in variability-driven optimization. [Citation Graph (0, 0)][DBLP]
    ISPD, 2006, pp:17-24 [Conf]
  14. Ashish Dobhal, Vishal Khandelwal, Azadeh Davoodi, Ankur Srivastava
    Variability Driven Joint Leakage-Delay Optimization Through Gate Sizing with Provabale Convergence. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:571-576 [Conf]
  15. Jennifer L. Wong, Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava, Miodrag Potkonjak
    A statistical methodology for wire-length prediction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:7, pp:1327-1336 [Journal]
  16. Azadeh Davoodi, Ankur Srivastava
    Voltage scheduling under unpredictabilities: a risk management paradigm. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:2, pp:354-368 [Journal]
  17. Azadeh Davoodi, Ankur Srivastava
    Effective techniques for the generalized low-power binding problem. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:1, pp:52-69 [Journal]
  18. Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava
    Empirical models for net-length probability distribution and applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:10, pp:1066-1075 [Journal]
  19. Azadeh Davoodi, Ankur Srivastava
    Power-driven simultaneous resource binding and floorplanning: a probabilistic approach. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:8, pp:934-942 [Journal]
  20. Vishal Khandelwal, Azadeh Davoodi, Ankur Srivastava
    Simultaneous V/sub t/ selection and assignment for leakage optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:6, pp:762-765 [Journal]
  21. Jungseob Lee, Azadeh Davoodi
    Comparison of Dual-Vt Configurations of SRAM Cell Considering Process-Induced Vt Variations. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3018-3021 [Conf]

  22. Bound-based identification of timing-violating paths under variability. [Citation Graph (, )][DBLP]


  23. GRIP: scalable 3D global routing using integer programming. [Citation Graph (, )][DBLP]


  24. Representative path selection for post-silicon timing prediction under variability. [Citation Graph (, )][DBLP]


  25. A parallel integer programming approach to global routing. [Citation Graph (, )][DBLP]


  26. Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variations. [Citation Graph (, )][DBLP]


  27. PaRS: fast and near-optimal grid-based cell sizing for library-based design. [Citation Graph (, )][DBLP]


  28. Adjustment-based modeling for statistical static timing analysis with high dimension of variability. [Citation Graph (, )][DBLP]


  29. Statistical timing analysis using Kernel smoothing. [Citation Graph (, )][DBLP]


  30. SynECO: Incremental technology mapping with constrained placement and fast detail routing for predictable timing improvement. [Citation Graph (, )][DBLP]


  31. A Dual-Vt low leakage SRAM array robust to process variations. [Citation Graph (, )][DBLP]


  32. A parallel and randomized algorithm for large-scale discrete dual-Vt assignment and continuous gate sizing. [Citation Graph (, )][DBLP]


  33. Statistical static timing analysis considering leakage variability in power gated designs. [Citation Graph (, )][DBLP]


  34. A pareto-algebraic framework for signal power optimization in global routing. [Citation Graph (, )][DBLP]


  35. Fast and Accurate Statistical Static Timing Analysis with Skewed Process Parameter Variation. [Citation Graph (, )][DBLP]


  36. Robust Estimation of Timing Yield with Partial Statistical Information on Process Variations. [Citation Graph (, )][DBLP]


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