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Ankur Srivastava: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Azadeh Davoodi, Ankur Srivastava
    Simultaneous floorplanning and resource binding: a probabilistic approach. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:517-522 [Conf]
  2. Azadeh Davoodi, Ankur Srivastava
    Wake-up protocols for controlling current surges in MTCMOS-based technology. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:868-871 [Conf]
  3. Ankur Srivastava, Chunhong Chen, Majid Sarrafzadeh
    Timing driven gate duplication in technology independent phase. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:577-582 [Conf]
  4. Azadeh Davoodi, Ankur Srivastava
    Variability driven gate sizing for binning yield optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:959-964 [Conf]
  5. Vishal Khandelwal, Ankur Srivastava
    A general framework for accurate statistical timing analysis considering correlations. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:89-94 [Conf]
  6. Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava
    High level techniques for power-grid noise immunity. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:13-18 [Conf]
  7. Abhishek Ranjan, Ankur Srivastava, V. Karnam, Majid Sarrafzadeh
    Layout aware retiming. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:25-30 [Conf]
  8. Lin Yuan, Gang Qu, Ankur Srivastava
    VLSI CAD tool protection by birthmarking design solutions. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:341-344 [Conf]
  9. Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava
    Variability inspired implementation selection problem. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:423-427 [Conf]
  10. Vishal Khandelwal, Azadeh Davoodi, Akash Nanavati, Ankur Srivastava
    A Probabilistic Approach to Buffer Insertion. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:560-567 [Conf]
  11. Vishal Khandelwal, Azadeh Davoodi, Ankur Srivastava
    Efficient statistical timing analysis through error budgeting. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:473-477 [Conf]
  12. Vishal Khandelwal, Ankur Srivastava
    Leakage control through fine-grained placement and sizing of sleep transistors. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:533-536 [Conf]
  13. Ankur Srivastava, Ryan Kastner, Majid Sarrafzadeh
    Timing Driven Gate Duplication: Complexity Issues and Algorithms. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:447-450 [Conf]
  14. Ankur Srivastava, Seda Ogrenci Memik, Bo-Kyung Choi, Majid Sarrafzadeh
    Achieving Design Closure Through Delay Relaxation Parameter. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:54-57 [Conf]
  15. Ankur Srivastava, Majid Sarrafzadeh
    Predictability: definition, ananlysis and optimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:118-121 [Conf]
  16. Jennifer L. Wong, Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava, Miodrag Potkonjak
    Wire-length prediction using statistical techniques. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:702-705 [Conf]
  17. Azadeh Davoodi, Ankur Srivastava
    Variability-Driven Buffer Insertion Considering Correlations. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:425-430 [Conf]
  18. Aswin C. Sankaranarayanan, Rama Chellappa, Ankur Srivastava
    Algorithmic and Architectural Design Methodology for Particle Filters in Hardware. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:275-280 [Conf]
  19. Azadeh Davoodi, Ankur Srivastava
    Effective graph theoretic techniques for the generalized low power binding problem. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:152-157 [Conf]
  20. Azadeh Davoodi, Ankur Srivastava
    Voltage scheduling under unpredictabilities: a risk management paradigm. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:302-305 [Conf]
  21. Azadeh Davoodi, Ankur Srivastava
    Probabilistic dual-Vth leakage optimization under variability. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:143-148 [Conf]
  22. Vishal Khandelwal, Ankur Srivastava
    Active mode leakage reduction using fine-grained forward body biasing strategy. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:150-155 [Conf]
  23. Eren Kursun, Ankur Srivastava, Seda Ogrenci Memik, Majid Sarrafzadeh
    Early evaluation techniques for low power binding. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:160-165 [Conf]
  24. Ankur Srivastava
    Simultaneous Vt selection and assignment for leakage optimization. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:146-151 [Conf]
  25. Azadeh Davoodi, Ankur Srivastava
    Probabilistic evaluation of solutions in variability-driven optimization. [Citation Graph (0, 0)][DBLP]
    ISPD, 2006, pp:17-24 [Conf]
  26. Majid Sarrafzadeh, Elaheh Bozorgzadeh, Ryan Kastner, Ankur Srivastava
    Design and analysis of physical design algorithms. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:82-89 [Conf]
  27. Ankur Srivastava, Majid Sarrafzadeh
    Predictability: Definition, Analysis and Optimization. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:267-272 [Conf]
  28. Ashish Dobhal, Vishal Khandelwal, Azadeh Davoodi, Ankur Srivastava
    Variability Driven Joint Leakage-Delay Optimization Through Gate Sizing with Provabale Convergence. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:571-576 [Conf]
  29. Ashish Dobhal, Vishal Khandelwal, Ankur Srivastava
    Efficient and Accurate Statistical Timing Analysis for Non-Linear Non-Gaussian Variability With Incremental Attributes. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:259-264 [Conf]
  30. Chunhong Chen, Elaheh Bozorgzadeh, Ankur Srivastava, Majid Sarrafzadeh
    Budget Management with Applications. [Citation Graph (0, 0)][DBLP]
    Algorithmica, 2002, v:34, n:3, pp:261-275 [Journal]
  31. Ankur Srivastava, Eren Kursun, Majid Sarrafzadeh
    Predictability in RT-Level Designs. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2002, v:11, n:4, pp:323-332 [Journal]
  32. Amir H. Farrahi, Chunhong Chen, Ankur Srivastava, Gustavo E. Téllez, Majid Sarrafzadeh
    Activity-driven clock design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:6, pp:705-714 [Journal]
  33. Ankur Srivastava, Ryan Kastner, Majid Sarrafzadeh
    On the complexity of gate duplication. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:9, pp:1170-1176 [Journal]
  34. Ankur Srivastava, Seda Ogrenci Memik, Bo-Kyung Choi, Majid Sarrafzadeh
    On effective slack management in postscheduling phase. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:4, pp:645-653 [Journal]
  35. Jennifer L. Wong, Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava, Miodrag Potkonjak
    A statistical methodology for wire-length prediction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:7, pp:1327-1336 [Journal]
  36. Azadeh Davoodi, Ankur Srivastava
    Voltage scheduling under unpredictabilities: a risk management paradigm. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:2, pp:354-368 [Journal]
  37. Azadeh Davoodi, Ankur Srivastava
    Effective techniques for the generalized low-power binding problem. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:1, pp:52-69 [Journal]
  38. Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava
    Empirical models for net-length probability distribution and applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:10, pp:1066-1075 [Journal]
  39. Azadeh Davoodi, Ankur Srivastava
    Power-driven simultaneous resource binding and floorplanning: a probabilistic approach. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:8, pp:934-942 [Journal]
  40. Vishal Khandelwal, Azadeh Davoodi, Ankur Srivastava
    Simultaneous V/sub t/ selection and assignment for leakage optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:6, pp:762-765 [Journal]
  41. Ankur Srivastava, Ryan Kastner, Chunhong Chen, Majid Sarrafzadeh
    Timing driven gate duplication. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:1, pp:42-51 [Journal]
  42. Vishal Khandelwal, Ankur Srivastava
    Variability-driven formulation for simultaneous gate sizing and post-silicon tunability allocation. [Citation Graph (0, 0)][DBLP]
    ISPD, 2007, pp:11-18 [Conf]
  43. Vishal Khandelwal, Ankur Srivastava
    Active mode leakage reduction using fine-grained forward body biasing strategy. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:4, pp:561-570 [Journal]
  44. Vishal Khandelwal, Ankur Srivastava
    A Quadratic Modeling-Based Framework for Accurate Statistical Timing Analysis Considering Correlations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:2, pp:206-215 [Journal]
  45. Chunhong Chen, Ankur Srivastava, Majid Sarrafzadeh
    On gate level power optimization using dual-supply voltages. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:5, pp:616-629 [Journal]

  46. Accurate temperature estimation using noisy thermal sensors. [Citation Graph (, )][DBLP]


  47. Adaptive and autonomous thermal tracking for high performance computing systems. [Citation Graph (, )][DBLP]


  48. Thermal-Aware Sensor Scheduling for Distributed Estimation. [Citation Graph (, )][DBLP]


  49. Monte-Carlo driven stochastic optimization framework for handling fabrication variability. [Citation Graph (, )][DBLP]


  50. Statistical timing analysis using Kernel smoothing. [Citation Graph (, )][DBLP]


  51. Chip level thermal profile estimation using on-chip temperature sensors. [Citation Graph (, )][DBLP]


  52. Dynamic thermal management for single and multicore processors under soft thermal constraints. [Citation Graph (, )][DBLP]


  53. Energy and thermal-aware video coding via encoder/decoder workload balancing. [Citation Graph (, )][DBLP]


  54. A statistical framework for designing on-chip thermal sensing infrastructure in nano-scale systems. [Citation Graph (, )][DBLP]


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