The SCEAS System
| |||||||

## Search the dblp DataBase
Ankur Srivastava:
[Publications]
[Author Rank by year]
[Co-authors]
[Prefers]
[Cites]
[Cited by]
## Publications of Author- Azadeh Davoodi, Ankur Srivastava
**Simultaneous floorplanning and resource binding: a probabilistic approach.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2005, pp:517-522 [Conf] - Azadeh Davoodi, Ankur Srivastava
**Wake-up protocols for controlling current surges in MTCMOS-based technology.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2005, pp:868-871 [Conf] - Ankur Srivastava, Chunhong Chen, Majid Sarrafzadeh
**Timing driven gate duplication in technology independent phase.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2001, pp:577-582 [Conf] - Azadeh Davoodi, Ankur Srivastava
**Variability driven gate sizing for binning yield optimization.**[Citation Graph (0, 0)][DBLP] DAC, 2006, pp:959-964 [Conf] - Vishal Khandelwal, Ankur Srivastava
**A general framework for accurate statistical timing analysis considering correlations.**[Citation Graph (0, 0)][DBLP] DAC, 2005, pp:89-94 [Conf] - Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava
**High level techniques for power-grid noise immunity.**[Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2004, pp:13-18 [Conf] - Abhishek Ranjan, Ankur Srivastava, V. Karnam, Majid Sarrafzadeh
**Layout aware retiming.**[Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2001, pp:25-30 [Conf] - Lin Yuan, Gang Qu, Ankur Srivastava
**VLSI CAD tool protection by birthmarking design solutions.**[Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2005, pp:341-344 [Conf] - Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava
**Variability inspired implementation selection problem.**[Citation Graph (0, 0)][DBLP] ICCAD, 2004, pp:423-427 [Conf] - Vishal Khandelwal, Azadeh Davoodi, Akash Nanavati, Ankur Srivastava
**A Probabilistic Approach to Buffer Insertion.**[Citation Graph (0, 0)][DBLP] ICCAD, 2003, pp:560-567 [Conf] - Vishal Khandelwal, Azadeh Davoodi, Ankur Srivastava
**Efficient statistical timing analysis through error budgeting.**[Citation Graph (0, 0)][DBLP] ICCAD, 2004, pp:473-477 [Conf] - Vishal Khandelwal, Ankur Srivastava
**Leakage control through fine-grained placement and sizing of sleep transistors.**[Citation Graph (0, 0)][DBLP] ICCAD, 2004, pp:533-536 [Conf] - Ankur Srivastava, Ryan Kastner, Majid Sarrafzadeh
**Timing Driven Gate Duplication: Complexity Issues and Algorithms.**[Citation Graph (0, 0)][DBLP] ICCAD, 2000, pp:447-450 [Conf] - Ankur Srivastava, Seda Ogrenci Memik, Bo-Kyung Choi, Majid Sarrafzadeh
**Achieving Design Closure Through Delay Relaxation Parameter.**[Citation Graph (0, 0)][DBLP] ICCAD, 2003, pp:54-57 [Conf] - Ankur Srivastava, Majid Sarrafzadeh
**Predictability: definition, ananlysis and optimization.**[Citation Graph (0, 0)][DBLP] ICCAD, 2002, pp:118-121 [Conf] - Jennifer L. Wong, Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava, Miodrag Potkonjak
**Wire-length prediction using statistical techniques.**[Citation Graph (0, 0)][DBLP] ICCAD, 2004, pp:702-705 [Conf] - Azadeh Davoodi, Ankur Srivastava
**Variability-Driven Buffer Insertion Considering Correlations.**[Citation Graph (0, 0)][DBLP] ICCD, 2005, pp:425-430 [Conf] - Aswin C. Sankaranarayanan, Rama Chellappa, Ankur Srivastava
**Algorithmic and Architectural Design Methodology for Particle Filters in Hardware.**[Citation Graph (0, 0)][DBLP] ICCD, 2005, pp:275-280 [Conf] - Azadeh Davoodi, Ankur Srivastava
**Effective graph theoretic techniques for the generalized low power binding problem.**[Citation Graph (0, 0)][DBLP] ISLPED, 2003, pp:152-157 [Conf] - Azadeh Davoodi, Ankur Srivastava
**Voltage scheduling under unpredictabilities: a risk management paradigm.**[Citation Graph (0, 0)][DBLP] ISLPED, 2003, pp:302-305 [Conf] - Azadeh Davoodi, Ankur Srivastava
**Probabilistic dual-Vth leakage optimization under variability.**[Citation Graph (0, 0)][DBLP] ISLPED, 2005, pp:143-148 [Conf] - Vishal Khandelwal, Ankur Srivastava
**Active mode leakage reduction using fine-grained forward body biasing strategy.**[Citation Graph (0, 0)][DBLP] ISLPED, 2004, pp:150-155 [Conf] - Eren Kursun, Ankur Srivastava, Seda Ogrenci Memik, Majid Sarrafzadeh
**Early evaluation techniques for low power binding.**[Citation Graph (0, 0)][DBLP] ISLPED, 2002, pp:160-165 [Conf] - Ankur Srivastava
**Simultaneous Vt selection and assignment for leakage optimization.**[Citation Graph (0, 0)][DBLP] ISLPED, 2003, pp:146-151 [Conf] - Azadeh Davoodi, Ankur Srivastava
**Probabilistic evaluation of solutions in variability-driven optimization.**[Citation Graph (0, 0)][DBLP] ISPD, 2006, pp:17-24 [Conf] - Majid Sarrafzadeh, Elaheh Bozorgzadeh, Ryan Kastner, Ankur Srivastava
**Design and analysis of physical design algorithms.**[Citation Graph (0, 0)][DBLP] ISPD, 2001, pp:82-89 [Conf] - Ankur Srivastava, Majid Sarrafzadeh
**Predictability: Definition, Analysis and Optimization.**[Citation Graph (0, 0)][DBLP] IWLS, 2002, pp:267-272 [Conf] - Ashish Dobhal, Vishal Khandelwal, Azadeh Davoodi, Ankur Srivastava
**Variability Driven Joint Leakage-Delay Optimization Through Gate Sizing with Provabale Convergence.**[Citation Graph (0, 0)][DBLP] VLSI Design, 2007, pp:571-576 [Conf] - Ashish Dobhal, Vishal Khandelwal, Ankur Srivastava
**Efficient and Accurate Statistical Timing Analysis for Non-Linear Non-Gaussian Variability With Incremental Attributes.**[Citation Graph (0, 0)][DBLP] VLSI Design, 2007, pp:259-264 [Conf] - Chunhong Chen, Elaheh Bozorgzadeh, Ankur Srivastava, Majid Sarrafzadeh
**Budget Management with Applications.**[Citation Graph (0, 0)][DBLP] Algorithmica, 2002, v:34, n:3, pp:261-275 [Journal] - Ankur Srivastava, Eren Kursun, Majid Sarrafzadeh
**Predictability in RT-Level Designs.**[Citation Graph (0, 0)][DBLP] Journal of Circuits, Systems, and Computers, 2002, v:11, n:4, pp:323-332 [Journal] - Amir H. Farrahi, Chunhong Chen, Ankur Srivastava, Gustavo E. Téllez, Majid Sarrafzadeh
**Activity-driven clock design.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:6, pp:705-714 [Journal] - Ankur Srivastava, Ryan Kastner, Majid Sarrafzadeh
**On the complexity of gate duplication.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:9, pp:1170-1176 [Journal] - Ankur Srivastava, Seda Ogrenci Memik, Bo-Kyung Choi, Majid Sarrafzadeh
**On effective slack management in postscheduling phase.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:4, pp:645-653 [Journal] - Jennifer L. Wong, Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava, Miodrag Potkonjak
**A statistical methodology for wire-length prediction.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:7, pp:1327-1336 [Journal] - Azadeh Davoodi, Ankur Srivastava
**Voltage scheduling under unpredictabilities: a risk management paradigm.**[Citation Graph (0, 0)][DBLP] ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:2, pp:354-368 [Journal] - Azadeh Davoodi, Ankur Srivastava
**Effective techniques for the generalized low-power binding problem.**[Citation Graph (0, 0)][DBLP] ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:1, pp:52-69 [Journal] - Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava
**Empirical models for net-length probability distribution and applications.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2004, v:12, n:10, pp:1066-1075 [Journal] - Azadeh Davoodi, Ankur Srivastava
**Power-driven simultaneous resource binding and floorplanning: a probabilistic approach.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2005, v:13, n:8, pp:934-942 [Journal] - Vishal Khandelwal, Azadeh Davoodi, Ankur Srivastava
**Simultaneous V/sub t/ selection and assignment for leakage optimization.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2005, v:13, n:6, pp:762-765 [Journal] - Ankur Srivastava, Ryan Kastner, Chunhong Chen, Majid Sarrafzadeh
**Timing driven gate duplication.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2004, v:12, n:1, pp:42-51 [Journal] - Vishal Khandelwal, Ankur Srivastava
**Variability-driven formulation for simultaneous gate sizing and post-silicon tunability allocation.**[Citation Graph (0, 0)][DBLP] ISPD, 2007, pp:11-18 [Conf] - Vishal Khandelwal, Ankur Srivastava
**Active mode leakage reduction using fine-grained forward body biasing strategy.**[Citation Graph (0, 0)][DBLP] Integration, 2007, v:40, n:4, pp:561-570 [Journal] - Vishal Khandelwal, Ankur Srivastava
**A Quadratic Modeling-Based Framework for Accurate Statistical Timing Analysis Considering Correlations.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2007, v:15, n:2, pp:206-215 [Journal] - Chunhong Chen, Ankur Srivastava, Majid Sarrafzadeh
**On gate level power optimization using dual-supply voltages.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2001, v:9, n:5, pp:616-629 [Journal] **Accurate temperature estimation using noisy thermal sensors.**[Citation Graph (, )][DBLP]**Adaptive and autonomous thermal tracking for high performance computing systems.**[Citation Graph (, )][DBLP]**Thermal-Aware Sensor Scheduling for Distributed Estimation.**[Citation Graph (, )][DBLP]**Monte-Carlo driven stochastic optimization framework for handling fabrication variability.**[Citation Graph (, )][DBLP]**Statistical timing analysis using Kernel smoothing.**[Citation Graph (, )][DBLP]**Chip level thermal profile estimation using on-chip temperature sensors.**[Citation Graph (, )][DBLP]**Dynamic thermal management for single and multicore processors under soft thermal constraints.**[Citation Graph (, )][DBLP]**Energy and thermal-aware video coding via encoder/decoder workload balancing.**[Citation Graph (, )][DBLP]**A statistical framework for designing on-chip thermal sensing infrastructure in nano-scale systems.**[Citation Graph (, )][DBLP]
Search in 0.017secs, Finished in 0.020secs | |||||||

| |||||||

| |||||||

System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002 for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002 |