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## Search the dblp DataBase
Tsutomu Sasao:
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## Publications of Author- Debatosh Debnath, Tsutomu Sasao
**Exact minimization of fixed polarity Reed-Muller expressions for incompletely specified functions.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2000, pp:247-252 [Conf] - Debatosh Debnath, Tsutomu Sasao
**Efficient computation of canonical form for Boolean matching in large libraries.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2004, pp:591-596 [Conf] - Debatosh Debnath, Tsutomu Sasao
**GRMIN: a heuristic simplification algorithm for generalized Reed-Muller expressions.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 1995, pp:- [Conf] - Debatosh Debnath, Tsutomu Sasao
**A Heuristic Algorithm to Design AND-OR-EXOR Three-Level Networks.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 1998, pp:69-74 [Conf] - Debatosh Debnath, Tsutomu Sasao
**Fast Boolean Matching Under Permutation Using Representative.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 1999, pp:359-362 [Conf] - Yukihiro Iguchi, Munehiro Matsuura, Tsutomu Sasao, Atsumu Iseno
**Realization of Regular Ternary Logic Functions.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 1999, pp:331-0 [Conf] - Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura, Atsumu Iseno
**A hardware simulation engine based on decision diagrams (short paper).**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2000, pp:73-76 [Conf] - Shinobu Nagayama, Tsutomu Sasao
**Minimization of memory size for heterogeneous MDDs.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2004, pp:871-874 [Conf] - Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
**Programmable numerical function generators based on quadratic approximation: architecture and synthesis method.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2006, pp:378-383 [Conf] - Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
**A fast logic simulator using a look up table cascade emulator.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2006, pp:466-472 [Conf] - Radomir S. Stankovic, Tsutomu Sasao
**Decision Diagrams for Discrete Functions: Classification and Unified Interpretation.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 1998, pp:439-446 [Conf] - Tsutomu Sasao, Jon T. Butler
**On the minimization of SOPs for bi-decomposition functions.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2001, pp:219-224 [Conf] - Tsutomu Sasao, Jon T. Butler
**A fast method to derive minimum SOPs for decomposable functions.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2004, pp:585-590 [Conf] - Tsutomu Sasao, Ken-ichi Kurimoto
**Three parameters to find functional decompositions.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2000, pp:259-264 [Conf] - Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura
**On Decomposition of Kleene TDDs.**[Citation Graph (0, 0)][DBLP] Asian Test Symposium, 1997, pp:234-0 [Conf] - Seiji Kajihara, Tsutomu Sasao
**On the Adders with Minimum Tests.**[Citation Graph (0, 0)][DBLP] Asian Test Symposium, 1997, pp:10-15 [Conf] - Alan Mishchenko, Tsutomu Sasao
**Large-scale SOP minimization using decomposition and functional properties.**[Citation Graph (0, 0)][DBLP] DAC, 2003, pp:149-154 [Conf] - Tsutomu Sasao
**MACDAS: multi-level AND-OR circuit synthesis using two-variable function generators.**[Citation Graph (0, 0)][DBLP] DAC, 1986, pp:86-93 [Conf] - Tsutomu Sasao, Munehiro Matsuura
**A method to decompose multiple-output logic functions.**[Citation Graph (0, 0)][DBLP] DAC, 2004, pp:428-433 [Conf] - Tsutomu Sasao, Munehiro Matsuura
**BDD representation for incompletely specifiedvmultiple-output logic functions and its applications to functional decomposition.**[Citation Graph (0, 0)][DBLP] DAC, 2005, pp:373-378 [Conf] - Tsutomu Sasao, Yukihiro Iguchi, Takahiro Suzuki
**On LUT Cascade Realizations of FIR Filters.**[Citation Graph (0, 0)][DBLP] DSD, 2005, pp:467-475 [Conf] - Tsutomu Sasao, Shinobu Nagayama, Jon T. Butler
**Programmable Numerical Function Generators: Architectures and Synthesis Method.**[Citation Graph (0, 0)][DBLP] FPL, 2005, pp:118-123 [Conf] - Hui Qin, Tsutomu Sasao, Yukihiro Iguchi
**An FPGA design of AES encryption circuit with 128-bit keys.**[Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2005, pp:147-151 [Conf] - Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura
**Realization of Multiple-Output Functions by Reconfigurable Cascades.**[Citation Graph (0, 0)][DBLP] ICCD, 2001, pp:388-393 [Conf] - Jon T. Butler, Tsutomu Sasao
**Multiple-Valued Combinational Circuits with Feedback.**[Citation Graph (0, 0)][DBLP] ISMVL, 1994, pp:342-347 [Conf] - Jon T. Butler, J. L. Nowlin, Tsutomu Sasao
**Planarity in ROMDD's of Multiple-Valued Symmetric Functions.**[Citation Graph (0, 0)][DBLP] ISMVL, 1996, pp:236-241 [Conf] - Jon T. Butler, Tsutomu Sasao
**On the Average Path Length in Decision Diagrams of Multiple-Valued Functions.**[Citation Graph (0, 0)][DBLP] ISMVL, 2003, pp:383-390 [Conf] - Jon T. Butler, Tsutomu Sasao
**On the Properties of Multiple-Valued Functions that are Symmetric in both Variable Values and Labels.**[Citation Graph (0, 0)][DBLP] ISMVL, 1998, pp:83-88 [Conf] - Hafiz Md. Hasan Babu, Tsutomu Sasao
**Representations of Multiple-Output Switching Functions Using Multiple-Valued Pseudo-Kronecker Decision Diagrams.**[Citation Graph (0, 0)][DBLP] ISMVL, 2000, pp:147-152 [Conf] - Hafiz Md. Hasan Babu, Tsutomu Sasao
**Design of Multiple-Output Networks using Time Domain Multiplexing and Shared Multi-Terminal Multiple-Valued Decision Diagrams.**[Citation Graph (0, 0)][DBLP] ISMVL, 1998, pp:45-51 [Conf] - Hafiz Md. Hasan Babu, Tsutomu Sasao
**Shared Multiple-Valued Decision Diagrams for Multiple-Output Functions.**[Citation Graph (0, 0)][DBLP] ISMVL, 1999, pp:166-172 [Conf] - Debatosh Debnath, Tsutomu Sasao
**Multiple-Valued Minimization to Optimize PLAs with Output EXOR Gates.**[Citation Graph (0, 0)][DBLP] ISMVL, 1999, pp:99-104 [Conf] - Yukihiro Iguchi, Tsutomu Sasao
**Hardware to Compute Walsh Coefficients.**[Citation Graph (0, 0)][DBLP] ISMVL, 2005, pp:75-81 [Conf] - Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura
**Implementation of Multiple-Output Functions Using PQMDDs.**[Citation Graph (0, 0)][DBLP] ISMVL, 2000, pp:199-205 [Conf] - Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura
**A Method to Evaluate Logic Functions in the Presence of Unknown Inputs Using LUT Cascades.**[Citation Graph (0, 0)][DBLP] ISMVL, 2004, pp:302-308 [Conf] - Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura
**On Designs of Radix Converters Using Arithmetic Decompositions.**[Citation Graph (0, 0)][DBLP] ISMVL, 2006, pp:3- [Conf] - Shinobu Nagayama, Tsutomu Sasao
**Compact Representations of Logic Functions using Heterogeneous MDDs.**[Citation Graph (0, 0)][DBLP] ISMVL, 2003, pp:247-252 [Conf] - Shinobu Nagayama, Tsutomu Sasao
**On the Minimization of Average Path Lengths for Heterogeneous MDDs.**[Citation Graph (0, 0)][DBLP] ISMVL, 2004, pp:216-222 [Conf] - Shinobu Nagayama, Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura
**Representations of Logic Functions Using QRMDDs.**[Citation Graph (0, 0)][DBLP] ISMVL, 2002, pp:261-0 [Conf] - Marek A. Perkowski, Tsutomu Sasao, Jong-Hwan Kim, Martin Lukac, Jeff Allen, Stefan Gebauer
**Hahoe KAIST Robot Theatre: Learning Rules of Interactive Robot Behavior as a Multiple-Valued Logic Synthesis Problem.**[Citation Graph (0, 0)][DBLP] ISMVL, 2005, pp:236-248 [Conf] - Tsutomu Sasao
**On the Number of Dependent Variables for Incompletely Specified Multiple-Valued Functions.**[Citation Graph (0, 0)][DBLP] ISMVL, 2000, pp:91-0 [Conf] - Tsutomu Sasao
**Compact SOP Representations for Multiple-Output Functions: An Encoding Method Using Multiple-Valued Logic.**[Citation Graph (0, 0)][DBLP] ISMVL, 2001, pp:207-212 [Conf] - Tsutomu Sasao
**Cascade Realizations of Two-valued Input Multiple-Valued Output Functions using Decomposition of Group Functions.**[Citation Graph (0, 0)][DBLP] ISMVL, 2003, pp:125-132 [Conf] - Tsutomu Sasao
**Radix Converters: Complexity and Implementation by LUT Cascades.**[Citation Graph (0, 0)][DBLP] ISMVL, 2005, pp:256-263 [Conf] - Tsutomu Sasao
**Design Methods for Multiple-Valued Input Address Generators.**[Citation Graph (0, 0)][DBLP] ISMVL, 2006, pp:1- [Conf] - Tsutomu Sasao
**EXMIN: A Simplification Algorithm for Exclusive-OR-Sum-of-Products Expressions for Multiple-Valued Input Two-Valued Output Functions.**[Citation Graph (0, 0)][DBLP] ISMVL, 1990, pp:128-135 [Conf] - Tsutomu Sasao
**A Transformation of Multiple-Valued Input Two-Valued Output Functions and its Application to Simplification of Exclusive-or Sum-of-Products Expressions.**[Citation Graph (0, 0)][DBLP] ISMVL, 1991, pp:270-279 [Conf] - Tsutomu Sasao
**Optimization of Multiple-Valued AND-EXOR Expressions Using Multiple-Place Decision Diagrams.**[Citation Graph (0, 0)][DBLP] ISMVL, 1992, pp:451-458 [Conf] - Tsutomu Sasao
**Ternary Decision Diagrams: Survey.**[Citation Graph (0, 0)][DBLP] ISMVL, 1997, pp:241-0 [Conf] - Tsutomu Sasao
**Totally Undecomposable Functions: Applications to Efficient Multiple-Valued Decompositions.**[Citation Graph (0, 0)][DBLP] ISMVL, 1999, pp:59-65 [Conf] - Tsutomu Sasao, Jon T. Butler
**Implementation of Multiple-Valued CAM Functions by LUT Cascades.**[Citation Graph (0, 0)][DBLP] ISMVL, 2006, pp:11- [Conf] - Tsutomu Sasao, Jon T. Butler
**Planar Multiple-Valued Decision Diagrams.**[Citation Graph (0, 0)][DBLP] ISMVL, 1995, pp:28-35 [Conf] - Tsutomu Sasao, Jon T. Butler
**A Method to Represent Multiple-Output Switching Functions by Using Multi-Valued Decision Diagrams.**[Citation Graph (0, 0)][DBLP] ISMVL, 1996, pp:248-254 [Conf] - Tsutomu Sasao, Jon T. Butler
**Comparison of the Worst and Best Sum-of-Products Expressions for Multiple-Valued Functions.**[Citation Graph (0, 0)][DBLP] ISMVL, 1997, pp:55-60 [Conf] - Tsutomu Sasao, Shinobu Nagayama
**Representations of Elementary Functions Using Binary Moment Diagrams.**[Citation Graph (0, 0)][DBLP] ISMVL, 2006, pp:28- [Conf] - Tsutomu Sasao, Jon T. Butler
**A Design Method for Look-up Table Type FPGA by Pseudo-Kronecker Expansion.**[Citation Graph (0, 0)][DBLP] ISMVL, 1994, pp:97-106 [Conf] - Radomir S. Stankovic, Milena Stankovic, Claudio Moraga, Tsutomu Sasao
**Calculation of Reed-Muller-Fourier Coefficients of Multiple-Valued Functions through Multiple-Place Decision Diagrams.**[Citation Graph (0, 0)][DBLP] ISMVL, 1994, pp:82-88 [Conf] - Atsushi Murakami, Seiji Kajihara, Tsutomu Sasao, Irith Pomeranz, Sudhakar M. Reddy
**Selection of potentially testable path delay faults for test generation.**[Citation Graph (0, 0)][DBLP] ITC, 2000, pp:376-384 [Conf] - Alan Mishchenko, Tsutomu Sasao
**Encoding of Boolean Functions and its Application to LUT Cascade Synthesis.**[Citation Graph (0, 0)][DBLP] IWLS, 2002, pp:115-120 [Conf] - Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura
**Comparison of Decision Diagrams for Multiple-Output Logic Functions.**[Citation Graph (0, 0)][DBLP] IWLS, 2002, pp:379-384 [Conf] - Tsutomu Sasao
**Multiple-Valued Logic and Optimization of Programmable Logic Arrays.**[Citation Graph (0, 0)][DBLP] IEEE Computer, 1988, v:21, n:4, pp:71-80 [Journal] - Daniel Brand, Tsutomu Sasao
**Minimization of AND-EXOR Expressions Using Rewrite Rules.**[Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 1993, v:42, n:5, pp:568-576 [Journal] - Jon T. Butler, David S. Herscovici, Tsutomu Sasao, Robert J. Barton III
**Average an Worst Case Number of Nodes in Decision Diagrams of Symmetric Multiple-Valued Functions.**[Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 1997, v:46, n:4, pp:491-494 [Journal] - Jon T. Butler, Tsutomu Sasao, Munehiro Matsuura
**Average Path Length of Binary Decision Diagrams.**[Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 2005, v:54, n:9, pp:1041-1053 [Journal] - Hideo Fujiwara, Yoich Nagao, Tsutomu Sasao, Kozo Kinoshita
**Easily Testable Sequential Machines with Extra Inputs.**[Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 1975, v:24, n:8, pp:821-826 [Journal] - Kozo Kinoshita, Tsutomu Sasao, Jun Matsuda
**On Magnetic Bubble Logic Circuits.**[Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 1976, v:25, n:3, pp:247-253 [Journal] - Tsutomu Sasao
**Multiple-Valued Decomposition of Generalized Boolean Functions and the Complexity of Programmable Logic Arrays.**[Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 1981, v:30, n:9, pp:635-643 [Journal] - Tsutomu Sasao
**Input Variable Assignment and Output Phase Optimization of PLA's.**[Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 1984, v:33, n:10, pp:879-894 [Journal] - Tsutomu Sasao
**An Algorithm to Derive the Complement of a Binary Function with Multiple-Valued Inputs.**[Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 1985, v:34, n:2, pp:131-140 [Journal] - Tsutomu Sasao
**On the Optimal Design of Multiple-Valued PLA's.**[Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 1989, v:38, n:4, pp:582-592 [Journal] - Tsutomu Sasao
**Bounds on the Average Number of Products in the Minimum Sum-of-Products Expressions for Multiple-Valued Input Two-Valued Output Functions.**[Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 1991, v:40, n:5, pp:645-651 [Journal] - Tsutomu Sasao
**Easily Testable Realizations for Generalized Reed-Muller Expressions.**[Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 1997, v:46, n:6, pp:709-716 [Journal] - Tsutomu Sasao, Jon T. Butler
**Worst and Best Irredundant Sum-of-Products Expressions.**[Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 2001, v:50, n:9, pp:935-948 [Journal] - Tsutomu Sasao, Kozo Kinoshita
**Realization of Minimum Circuits with Two-Input Conservative Logic Elements.**[Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 1978, v:27, n:8, pp:749-752 [Journal] - Tsutomu Sasao, Kozo Kinoshita
**Cascade Realization of 3-Input 3-Output Conservative Logic Circuits.**[Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 1978, v:27, n:3, pp:214-221 [Journal] - Tsutomu Sasao, Kozo Kinoshita
**Conservative Logic Elements and Their Universality.**[Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 1979, v:28, n:9, pp:682-685 [Journal] - Tsutomu Sasao, Kozo Kinoshita
**On the Number of Fanout-Free Functions and Unate Cascade Functions.**[Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 1979, v:28, n:1, pp:66-72 [Journal] - Tsutomu Sasao, Shinobu Nagayama, Jon T. Butler
**Numerical Function Generators Using LUT Cascades.**[Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 2007, v:56, n:6, pp:826-838 [Journal] - Shinobu Nagayama, Tsutomu Sasao
**On the optimization of heterogeneous MDDs.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:11, pp:1645-1659 [Journal] - Tsutomu Sasao
**EXMIN2: a simplification algorithm for exclusive-OR-sum-of-products expressions for multiple-valued-input two-valued-output functions.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:5, pp:621-632 [Journal] - Radomir S. Stankovic, Tsutomu Sasao
**A discussion on the history of research in arithmetic andReed-Muller expressions.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:9, pp:1177-1179 [Journal] - Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
**A CAM Emulator Using Look-Up Table Cascades.**[Citation Graph (0, 0)][DBLP] IPDPS, 2007, pp:1-8 [Conf] - Hui Qin, Tsutomu Sasao, Jon T. Butler
**Implementation of LPM Address Generators on FPGAs.**[Citation Graph (0, 0)][DBLP] ARC, 2006, pp:170-181 [Conf] **Numerical Function Generators Using Edge-Valued Binary Decision Diagrams.**[Citation Graph (, )][DBLP]**Design Method for Numerical Function Generators Based on Polynomial Approximation for FPGA Implementation.**[Citation Graph (, )][DBLP]**An Implementation of an Address Generator Using Hash Memories.**[Citation Graph (, )][DBLP]**On the Complexity of Error Detection Functions for Redundant Residue Number Systems.**[Citation Graph (, )][DBLP]**Programmable Numerical Function Generators for Two-Variable Functions.**[Citation Graph (, )][DBLP]**Representation of Incompletely Specified Index Generation Functions Using Minimal Number of Compound Variables.**[Citation Graph (, )][DBLP]**The Parallel Sieve Method for a Virus Scanning Engine.**[Citation Graph (, )][DBLP]**Numerical function generators using bilinear interpolation.**[Citation Graph (, )][DBLP]**A virus scanning engine using a parallel finite-input memory machine and MPUs.**[Citation Graph (, )][DBLP]**On the numbers of variables to represent sparse logic functions.**[Citation Graph (, )][DBLP]**An Application of 16-Valued Logic to Design of Reconfigurable Logic Arrays.**[Citation Graph (, )][DBLP]**On Designs of Radix Converters Using Arithmetic Decompositions--Binary to Decimal Converters--.**[Citation Graph (, )][DBLP]**On the Complexity of Classification Functions.**[Citation Graph (, )][DBLP]**Representations of Two-Variable Elementary Functions Using EVMDDs and their Applications to Function Generators.**[Citation Graph (, )][DBLP]**Representations of Elementary Functions Using Edge-Valued MDDs.**[Citation Graph (, )][DBLP]**Floating-Point Numerical Function Generators Using EVMDDs for Monotone Elementary Functions.**[Citation Graph (, )][DBLP]**A Quaternary Decision Diagram Machine and the Optimization of its Code.**[Citation Graph (, )][DBLP]**On the Number of Products to Represent Interval Functions by SOPs with Four-Valued Variables.**[Citation Graph (, )][DBLP]**Floating-Point Numeric Function Generators Based on Piecewise-Split EVMDDs.**[Citation Graph (, )][DBLP]**A Comparison of Architectures for Various Decision Diagram Machines.**[Citation Graph (, )][DBLP]**A Parallel Branching Program Machine for Emulation of Sequential Circuits.**[Citation Graph (, )][DBLP]
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