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Chris C. N. Chu: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Sampath Dechu, Zion Cien Shen, Chris C. N. Chu
    An efficient routing tree construction algorithm with buffer insertion, wire sizing and obstacle considerations. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:361-366 [Conf]
  2. Zion Cien Shen, Chris C. N. Chu
    Accurate and efficient flow based congestion estimation in floorplanning. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:671-676 [Conf]
  3. Natarajan Viswanathan, Min Pan, Chris C. N. Chu
    FastPlace 2.0: an efficient analytical placer for mixed-mode designs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:195-200 [Conf]
  4. Evangeline F. Y. Young, M. L. Ho, Chris C. N. Chu
    A Unified Method to Handle Different Kinds of Placement Constraints in Floorplan Design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:661-670 [Conf]
  5. Chiu-Wing Sham, Evangeline F. Y. Young, Chris C. N. Chu
    Optimal cell flipping in placement and floorplanning. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:1109-1114 [Conf]
  6. Chris C. N. Chu, D. F. Wong
    A Polynomial Time Optimal Algorithm for Simultaneous Buffer and Wire Sizing. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:479-0 [Conf]
  7. Chris C. N. Chu, Evangeline F. Y. Young
    Non-Rectangular Shaping and Sizing of Soft Modules in Floorplan Design. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1101- [Conf]
  8. Steve T. W. Lai, Evangeline F. Y. Young, Chris C. N. Chu
    A New and Efficient Congestion Evaluation Model in Floorplanning: Wire Density Control with Twin Binary Trees. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10856-10861 [Conf]
  9. Chung-Ping Chen, Chris C. N. Chu, D. F. Wong
    Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:617-624 [Conf]
  10. Chris C. N. Chu, D. F. Wong
    A new approach to simultaneous buffer insertion and wire sizing. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:614-621 [Conf]
  11. Chris C. N. Chu, Evangeline F. Y. Young, Dennis K. Y. Tong, Sampath Dechu
    Retiming with Interconnect and Gate Delay. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:221-226 [Conf]
  12. Min Pan, Natarajan Viswanathan, Chris C. N. Chu
    An efficient and effective detailed placement algorithm. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:48-55 [Conf]
  13. Yiu-Cheong Tam, Evangeline F. Y. Young, Chris C. N. Chu
    Analog placement with symmetry and other placement constraints. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:349-354 [Conf]
  14. Royce L. S. Ching, Evangeline F. Y. Young, Kevin C. K. Leung, Chris Chu
    Post-placement voltage island generation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:641-646 [Conf]
  15. Chuan Lin, Hai Zhou, Chris Chu
    A revisit to floorplan optimization by Lagrangian relaxation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:164-171 [Conf]
  16. Min Pan, Chris C. N. Chu
    FastRoute: a step to integrate global routing into placement. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:464-471 [Conf]
  17. Arif Ishaq Abou-Seido, Brian Nowak, Chris C. N. Chu
    Fitted Elmore Delay: A Simple and Accurate Interconnect Delay Model. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:422-427 [Conf]
  18. Zion Cien Shen, Chris C. N. Chu, Ying-Meng Li
    Efficient Rectilinear Steiner Tree Construction with Rectilinear Blockages. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:38-44 [Conf]
  19. Min Pan, Chris C. N. Chu, J. Morris Chang
    Transition time bounded low-power clock tree construction. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2445-2448 [Conf]
  20. Min Pan, Chris C. N. Chu, Hai Zhou
    Timing yield estimation using statistical static timing analysis. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2461-2464 [Conf]
  21. Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay
    Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. [Citation Graph (0, 0)][DBLP]
    ISPD, 2002, pp:104-109 [Conf]
  22. Yu-Yen Mo, Chris C. N. Chu
    A hybrid dynamic/quadratic programming algorithm for interconnect tree optimization. [Citation Graph (0, 0)][DBLP]
    ISPD, 2000, pp:134-139 [Conf]
  23. Chris C. N. Chu, Yiu-Chung Wong
    Fast and accurate rectilinear steiner minimal tree algorithm for VLSI design. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:28-35 [Conf]
  24. Chris C. N. Chu, D. F. Wong
    A matrix synthesis approach to thermal placement. [Citation Graph (0, 0)][DBLP]
    ISPD, 1997, pp:163-168 [Conf]
  25. Chris C. N. Chu, D. F. Wong
    Closed form solution to simultaneous buffer insertion/sizing and wire sizing. [Citation Graph (0, 0)][DBLP]
    ISPD, 1997, pp:192-197 [Conf]
  26. Chris C. N. Chu, D. F. Wong
    Greedy wire-sizing is linear time. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:39-44 [Conf]
  27. Debjit Sinha, Hai Zhou, Chris C. N. Chu
    Optimal gate sizing for coupling-noise reduction. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:176-181 [Conf]
  28. Natarajan Viswanathan, Chris C. N. Chu
    FastPlace: efficient analytical placement using cell shifting, iterative local refinement and a hybrid net model. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:26-33 [Conf]
  29. Natarajan Viswanathan, Min Pan, Chris C. N. Chu
    FastPlace: an analytical placer for mixed-mode designs. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:221-223 [Conf]
  30. Fung Yu Young, Chris C. N. Chu, W. S. Luk, Y. C. Wong
    Floorplan area minimization using Lagrangian relaxation. [Citation Graph (0, 0)][DBLP]
    ISPD, 2000, pp:174-179 [Conf]
  31. Evangeline F. Y. Young, Chris C. N. Chu, Zion Cien Shen
    Twin binary sequences: a non-redundant representation for general non-slicing floorplan. [Citation Graph (0, 0)][DBLP]
    ISPD, 2002, pp:196-201 [Conf]
  32. Evangeline F. Y. Young, Chris C. N. Chu, M. L. Ho
    A Unified Method to Handle Different Kinds of Placement Constraints in Floorplan Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:661-0 [Conf]
  33. Fung Yu Young, Chris C. N. Chu, D. F. Wong
    Generation of Universal Series-Parallel Boolean Functions. [Citation Graph (0, 0)][DBLP]
    J. ACM, 1999, v:46, n:3, pp:416-435 [Journal]
  34. Daniel Berleant, Mei-Peng Cheong, Chris C. N. Chu, Yong Guan, Ahmed Kamal, Gerald Shedblé, Scott Ferson, James F. Peters
    Dependable Handling of Uncertainty. [Citation Graph (0, 0)][DBLP]
    Reliable Computing, 2003, v:9, n:6, pp:407-418 [Journal]
  35. Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay
    Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:1, pp:136-141 [Journal]
  36. Chung-Ping Chen, Chris C. N. Chu, Martin D. F. Wong
    Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:7, pp:1014-1025 [Journal]
  37. Chris C. N. Chu, Martin D. F. Wong
    A matrix synthesis approach to thermal placement. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:11, pp:1166-1174 [Journal]
  38. Chris C. N. Chu, Martin D. F. Wong
    Greedy wire-sizing is linear time. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:4, pp:398-405 [Journal]
  39. Chris C. N. Chu, Martin D. F. Wong
    A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:6, pp:787-798 [Journal]
  40. Chris C. N. Chu, Martin D. F. Wong
    An efficient and optimal algorithm for simultaneous buffer and wire sizing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:9, pp:1297-1304 [Journal]
  41. Chris C. N. Chu, Evangeline F. Y. Young
    Nonrectangular shaping and sizing of soft modules for floorplan-design improvement. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:1, pp:71-79 [Journal]
  42. Sampath Dechu, Zion Cien Shen, Chris C. N. Chu
    An efficient routing tree construction algorithm with buffer insertion, wire sizing, and obstacle considerations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:4, pp:600-608 [Journal]
  43. Yu-Yen Mo, Chris C. N. Chu
    Hybrid dynamic/quadratic programming algorithm for interconnecttree optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:5, pp:680-686 [Journal]
  44. Zion Cien Shen, Chris C. N. Chu
    Bounds on the number of slicing, mosaic, and general floorplans. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:10, pp:1354-1361 [Journal]
  45. Natarajan Viswanathan, Chris C. N. Chu
    FastPlace: efficient analytical placement using cell shifting, iterative local refinement, and a hybrid net model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:5, pp:722-733 [Journal]
  46. Evangeline F. Y. Young, Chris C. N. Chu, W. S. Luk, Y. C. Wong
    Handling soft modules in general nonslicing floorplan usingLagrangian relaxation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:5, pp:687-692 [Journal]
  47. Evangeline F. Y. Young, Chris C. N. Chu, Zion Cien Shen
    Twin binary sequences: a nonredundant representation for general nonslicing floorplan. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:4, pp:457-469 [Journal]
  48. Chris C. N. Chu, D. F. Wong
    Closed form solutions to simultaneous buffer insertion/sizing and wire sizing. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2001, v:6, n:3, pp:343-371 [Journal]
  49. Evangeline F. Y. Young, Chris C. N. Chu, M. L. Ho
    Placement constraints in floorplan design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:7, pp:735-745 [Journal]
  50. Min Pan, Chris Chu
    IPR: An Integrated Placement and Routing Algorithm. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:59-62 [Conf]
  51. Natarajan Viswanathan, Gi-Joon Nam, Charles J. Alpert, Paul Villarrubia, Haoxing Ren, Chris Chu
    RQL: Global Placement via Relaxed Quadratic Spreading and Linearization. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:453-458 [Conf]

  52. FastRoute 2.0: A High-quality and Efficient Global Router. [Citation Graph (, )][DBLP]


  53. A Novel Performance-Driven Topology Design Algorithm. [Citation Graph (, )][DBLP]


  54. FastPlace 3.0: A Fast Multilevel Quadratic Placement Algorithm with Placement Congestion Control. [Citation Graph (, )][DBLP]


  55. The coming of age of physical synthesis. [Citation Graph (, )][DBLP]


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