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Vijay Degalahal: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Vijay Degalahal, Tim Tuan
    Methodology for high level estimation of FPGA power consumption. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:657-660 [Conf]
  2. Jie S. Hu, Feihui Li, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin
    Compiler-Directed Instruction Duplication for Soft Error Detection. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1056-1057 [Conf]
  3. Lin Li, Vijay Degalahal, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
    Soft error and energy consumption interactions: a data cache perspective. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:132-137 [Conf]
  4. Vijay Degalahal, R. Ramanarayanan, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin
    The Effect of Threshold Voltages on the Soft Error Rate. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:503-508 [Conf]
  5. Wei Zhang 0002, Jie S. Hu, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin
    Compiler-directed instruction cache leakage optimization. [Citation Graph (0, 0)][DBLP]
    MICRO, 2002, pp:208-218 [Conf]
  6. Vijay Degalahal, Narayanan Vijaykrishnan, Mary Jane Irwin
    Analyzing Soft Errors in Leakage Optimized SRAM Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:227-233 [Conf]
  7. Thomas D. Richardson, Chrysostomos Nicopoulos, Dongkook Park, Narayanan Vijaykrishnan, Yuan Xie, Chita R. Das, Vijay Degalahal
    A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:657-664 [Conf]
  8. Taylan Yemliha, Guangyu Chen, Ozcan Ozturk, Mahmut T. Kandemir, Vijay Degalahal
    Compiler-Directed Code Restructuring for Operating with Compressed Arrays. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:221-226 [Conf]
  9. Mahmut T. Kandemir, Ozcan Ozturk, Vijay Degalahal
    Enhancing Locality in Two-Dimensional Space through Integrated Computation and Data Mappings. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:227-232 [Conf]
  10. Wei Zhang 0002, Jie S. Hu, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin
    Reducing instruction cache energy consumption using a compiler-based strategy. [Citation Graph (0, 0)][DBLP]
    TACO, 2004, v:1, n:1, pp:3-33 [Journal]
  11. Vijay Degalahal, Lin Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
    Soft errors issues in low-power caches. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:10, pp:1157-1166 [Journal]

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