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Tetsushi Koide: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Takahiro Deguchi, Tetsushi Koide, Shin'ichi Wakabayashi
    Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:99-104 [Conf]
  2. Koichi Hatta, Shin'ichi Wakabayashi, Tetsushi Koide
    Solving the Rectangular Packing Problem by an Adaptive GA Based on Sequence-Pair. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:181-184 [Conf]
  3. Yoshinori Katsura, Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida
    A new system partitioning method under performance and physical constraints for multi-chip modules. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  4. Tetsushi Koide, Mitsuhiro Ono, Shin'ichi Wakabayashi, Yutaka Nishimaru
    A new performance driven placement method with the Elmore delay model for row based VLSIs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  5. Tetsushi Koide, Shin'ichi Wakabayashi
    A Timing-Driven Global Routing Algorithm with Pin Assignment, Block Reshaping, and Positioning for Building Block Layout. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:577-583 [Conf]
  6. Takashi Morimoto, Yohmei Harada, Tetsushi Koide, Hans Jürgen Mattausch
    350nm CMOS test-chip for architecture verification of real-time QVGA color-video segmentation at the 90nm technology node. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:531-532 [Conf]
  7. Takashi Morimoto, Osamu Kiriyama, Hidekazu Adachi, Zhaomin Zhu, Tetsushi Koide, Hans Jürgen Mattausch
    A low-power video segmentation LSI with boundary-active-only architecture. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:13-14 [Conf]
  8. Tetsuya Sueyoshi, Hiroshi Uchida, Hans Jürgen Mattausch, Tetsushi Koide, Yosuke Mitani, Tetsuo Hironaka
    Compact 12-port multi-bank register file test-chip in 0.35µm CMOS for highly parallel processors. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:551-552 [Conf]
  9. Masahiro Tsuchiya, Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida
    A three-layer over-cell multi-channel routing method for a new cell model. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  10. Shin'ichi Wakabayashi, Tetsushi Koide, Naoyoshi Toshine, Mutsuaki Goto, Yoshikatsu Nakayama, Koichi Hatta
    An LSI Implementation of an Adaptive Genetic Algorithm with On-The Fly Crossover Operator Selection. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:37-40 [Conf]
  11. Shin'ichi Wakabayashi, Tetsushi Koide, Nayoshi Toshine, Masataka Yamane, Hajime Ueno
    Genetic algorithm accelerator GAA-II. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:9-10 [Conf]
  12. K. Yamaoka, Takashi Morimoto, Hidekazu Adachi, Tetsushi Koide, Hans Jürgen Mattausch
    Image segmentation and pattern matching based FPGA/ASIC implementation architecture of real-time object tracking. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:176-181 [Conf]
  13. Yuji Yano, Tetsushi Koide, Hans Jürgen Mattausch
    Associative memory with fully parallel nearest-Manhattan-distance search for low-power real-time single-chip applications. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:543-544 [Conf]
  14. Tetsushi Koide, Yoshinori Katsura, Katsumi Yamatani, Shin'ichi Wakabayashi, Noriyoshi Yoshida
    A Floorplanning Method with Topological Constraint Manipulation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:165-168 [Conf]
  15. Takeshi Kumaki, Yasuto Kuroda, Tetsushi Koide, Hans Jürgen Mattausch, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito
    CAM-based VLSI architecture for Huffman coding with real-time optimization of the code word table [image coding example]. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5202-5205 [Conf]
  16. Tetsuya Miyoshi, Shin'ichi Wakabayashi, Tetsushi Koide, Noriyoshi Yoshida
    An MCM Routing Algorithm Considering Crosstalk. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:211-214 [Conf]
  17. Toshihiro Nakaoa, Shin'ichi Wakabayashi, Tetsushi Koide, Noriyoshi Yoshida
    A Verification Algorithm for Logic Circuits with Internal Variables. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:1920-1923 [Conf]
  18. Shin'ichi Wakabayashi, Kazunori Isomoto, Tetsushi Koide, Noriyoshi Yoshida
    A Systolic Graph Partitioning Algorithm for VLSI Design. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:225-228 [Conf]
  19. Shin'ichi Wakabayashi, Hiroshi Kusumoto, Hideki Mishima, Tetsushi Koide, Noriyoshi Yoshida
    Gate Array Placement Based on Mincut, Partitioning with Path Delay Constraints. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2059-2062 [Conf]
  20. Koichi Hatta, Masashige Suzuki, Shin'ichi Wakabayashi, Tetsushi Koide
    Solving the Capacitor Placement Problem in a Radial Distribution System Using an Adaptive Genetic Algorithm. [Citation Graph (0, 0)][DBLP]
    PPSN, 1998, pp:1028-1037 [Conf]
  21. Tetsushi Koide, S. Shinmori, H. Ishii
    Topological optimization with a network reliability constraint. [Citation Graph (0, 0)][DBLP]
    Discrete Applied Mathematics, 2001, v:115, n:1-3, pp:135-149 [Journal]
  22. Tetsushi Koide, Masahiro Tsuchiya, Shin'ichi Wakabayashi, Noriyoshi Yoshida
    A three-layer over-the-cell multi-channel router for a new cell model. [Citation Graph (0, 0)][DBLP]
    Integration, 1996, v:21, n:3, pp:171-189 [Journal]
  23. Tetsushi Koide, Shin'ichi Wakabayashi
    A timing-driven floorplanning algorithm with the Elmore delay model for building block layout. [Citation Graph (0, 0)][DBLP]
    Integration, 1999, v:27, n:1, pp:57-76 [Journal]
  24. Tetsushi Koide, Shin'ichi Wakabayashi, Mitsuhiro Ono, Yutaka Nishimaru, Noriyoshi Yoshida
    A timing-driven placement algorithm with the Elmore delay model for row-based VLSIs. [Citation Graph (0, 0)][DBLP]
    Integration, 1997, v:24, n:1, pp:53-77 [Journal]
  25. Koichi Hatta, Shin'ichi Wakabayashi, Tetsushi Koide
    Adaptation of genetic operators and parameters of a genetic algorithm based on the elite degree of an individual. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 2001, v:32, n:1, pp:29-37 [Journal]
  26. Takahiro Sasaki, Tomohiro Inoue, Nobuhiko Omori, Tetsuo Hironaka, Hans Jürgen Mattausch, Tetsushi Koide
    Chip size and performance evaluations of shared cache for on-chip multiprocessor. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 2005, v:36, n:9, pp:1-13 [Journal]
  27. Shigeki Takekawa, Shin'ichi Wakabayashi, Tetsushi Koide
    A coterie-based mutual exclusion algorithm for distributed systems allowing multiple process failures at arbitrary time. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 2002, v:33, n:12, pp:87-96 [Journal]
  28. Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida
    Pin assignment with global routing for VLSI building block layout. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:12, pp:1575-1583 [Journal]
  29. Takeshi Kumaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito
    Efficient Vertical/Horizontal-Space 1D-DCT Processing Based on Massive-Parallel Matrix-Processing Engine. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:525-528 [Conf]
  30. K. Yamaoka, Takashi Morimoto, Hidekazu Adachi, K. Awane, Tetsushi Koide, Hans Jürgen Mattausch
    Multi-object tracking VLSI architecture using image-scan based region growing and feature matching. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]

  31. A parallel hardware design for parametric active contour models. [Citation Graph (, )][DBLP]


  32. Design of superscalar processor with multi-bank register file. [Citation Graph (, )][DBLP]


  33. Object tracking in video pictures based on image segmentation and pattern matching. [Citation Graph (, )][DBLP]


  34. Unified Data/Instruction Cache with Hierarchical Multi-Port Architecture and Hidden Precharge Pipeline. [Citation Graph (, )][DBLP]


  35. Fully Parallel Associative Memory Architecture with Mixed Digital-Analog Match Circuit for Nearest Euclidean Distance Search. [Citation Graph (, )][DBLP]


  36. Application of Multi-ported CAM for Parallel Coding. [Citation Graph (, )][DBLP]


  37. An FPGA-Based Region-Growing Video Segmentation System with Boundary-Scan-Only LSI Architecture. [Citation Graph (, )][DBLP]


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