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Shin'ichi Wakabayashi: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Takahiro Deguchi, Tetsushi Koide, Shin'ichi Wakabayashi
    Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:99-104 [Conf]
  2. Koichi Hatta, Shin'ichi Wakabayashi, Tetsushi Koide
    Solving the Rectangular Packing Problem by an Adaptive GA Based on Sequence-Pair. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:181-184 [Conf]
  3. Yoshinori Katsura, Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida
    A new system partitioning method under performance and physical constraints for multi-chip modules. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  4. Tetsushi Koide, Mitsuhiro Ono, Shin'ichi Wakabayashi, Yutaka Nishimaru
    A new performance driven placement method with the Elmore delay model for row based VLSIs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  5. Tetsushi Koide, Shin'ichi Wakabayashi
    A Timing-Driven Global Routing Algorithm with Pin Assignment, Block Reshaping, and Positioning for Building Block Layout. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:577-583 [Conf]
  6. Masahiro Tsuchiya, Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida
    A three-layer over-cell multi-channel routing method for a new cell model. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  7. Shin'ichi Wakabayashi, Tetsushi Koide, Naoyoshi Toshine, Mutsuaki Goto, Yoshikatsu Nakayama, Koichi Hatta
    An LSI Implementation of an Adaptive Genetic Algorithm with On-The Fly Crossover Operator Selection. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:37-40 [Conf]
  8. Shin'ichi Wakabayashi, Tetsushi Koide, Nayoshi Toshine, Masataka Yamane, Hajime Ueno
    Genetic algorithm accelerator GAA-II. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:9-10 [Conf]
  9. Shin'ichi Wakabayashi, Kenji Kikuchi
    An Instance-Specific Hardware Algorithm for Finding a Maximum Clique. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:516-525 [Conf]
  10. Shin'ichi Wakabayashi, Kenji Kikuchi
    Solving the Minimum Dominating Set Problem with Instance-Specific Hardware on FPGAs. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:69-76 [Conf]
  11. Takeshi Fushimi, Yoko Kamidoi, Shin'ichi Wakabayashi
    An Algorithm for Computing Global-Based Outlier Degrees on Data Sets. [Citation Graph (0, 0)][DBLP]
    ICDE Workshops, 2005, pp:1224- [Conf]
  12. Tomotake Nakamura, Yoko Kamidoi, Shin'ichi Wakabayashi, Noriyoshi Yoshida
    Feature Extraction of Clusters Based on FlexDice. [Citation Graph (0, 0)][DBLP]
    ICDE Workshops, 2005, pp:1126- [Conf]
  13. Tomotake Nakamura, Yoko Kamidoi, Shin'ichi Wakabayashi, Noriyoshi Yoshida
    A Decision Method of Attribute Importance for Classification by Outlier Detection. [Citation Graph (0, 0)][DBLP]
    ICDE Workshops, 2006, pp:120- [Conf]
  14. Yoko Kamidoi, Shin'ichi Wakabayashi, Noriyoshi Yoshida
    On Three-Way Graph Partitioning. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:173-176 [Conf]
  15. Tetsushi Koide, Yoshinori Katsura, Katsumi Yamatani, Shin'ichi Wakabayashi, Noriyoshi Yoshida
    A Floorplanning Method with Topological Constraint Manipulation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:165-168 [Conf]
  16. Tetsuya Miyoshi, Shin'ichi Wakabayashi, Tetsushi Koide, Noriyoshi Yoshida
    An MCM Routing Algorithm Considering Crosstalk. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:211-214 [Conf]
  17. Toshihiro Nakaoa, Shin'ichi Wakabayashi, Tetsushi Koide, Noriyoshi Yoshida
    A Verification Algorithm for Logic Circuits with Internal Variables. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:1920-1923 [Conf]
  18. Shin'ichi Wakabayashi, Kazunori Isomoto, Tetsushi Koide, Noriyoshi Yoshida
    A Systolic Graph Partitioning Algorithm for VLSI Design. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:225-228 [Conf]
  19. Shin'ichi Wakabayashi, Hiroshi Kusumoto, Hideki Mishima, Tetsushi Koide, Noriyoshi Yoshida
    Gate Array Placement Based on Mincut, Partitioning with Path Delay Constraints. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2059-2062 [Conf]
  20. Koichi Hatta, Masashige Suzuki, Shin'ichi Wakabayashi, Tetsushi Koide
    Solving the Capacitor Placement Problem in a Radial Distribution System Using an Adaptive Genetic Algorithm. [Citation Graph (0, 0)][DBLP]
    PPSN, 1998, pp:1028-1037 [Conf]
  21. Tomotake Nakamura, Yoko Kamidoi, Shin'ichi Wakabayashi, Noriyoshi Yoshida
    A Clustering Method Using an Irregular Size Cell Graph. [Citation Graph (0, 0)][DBLP]
    RIDE, 2005, pp:19-26 [Conf]
  22. Yoko Kamidoi, Shin'ichi Wakabayashi, Noriyoshi Yoshida
    A Divide-and-Conquer Approach to the Minimum k-Way Cut Problem. [Citation Graph (0, 0)][DBLP]
    Algorithmica, 2002, v:32, n:2, pp:262-276 [Journal]
  23. Tetsushi Koide, Masahiro Tsuchiya, Shin'ichi Wakabayashi, Noriyoshi Yoshida
    A three-layer over-the-cell multi-channel router for a new cell model. [Citation Graph (0, 0)][DBLP]
    Integration, 1996, v:21, n:3, pp:171-189 [Journal]
  24. Tetsushi Koide, Shin'ichi Wakabayashi
    A timing-driven floorplanning algorithm with the Elmore delay model for building block layout. [Citation Graph (0, 0)][DBLP]
    Integration, 1999, v:27, n:1, pp:57-76 [Journal]
  25. Tetsushi Koide, Shin'ichi Wakabayashi, Mitsuhiro Ono, Yutaka Nishimaru, Noriyoshi Yoshida
    A timing-driven placement algorithm with the Elmore delay model for row-based VLSIs. [Citation Graph (0, 0)][DBLP]
    Integration, 1997, v:24, n:1, pp:53-77 [Journal]
  26. Koichi Hatta, Shin'ichi Wakabayashi, Tetsushi Koide
    Adaptation of genetic operators and parameters of a genetic algorithm based on the elite degree of an individual. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 2001, v:32, n:1, pp:29-37 [Journal]
  27. Shigeki Takekawa, Shin'ichi Wakabayashi, Tetsushi Koide
    A coterie-based mutual exclusion algorithm for distributed systems allowing multiple process failures at arbitrary time. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 2002, v:33, n:12, pp:87-96 [Journal]
  28. Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida
    Pin assignment with global routing for VLSI building block layout. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:12, pp:1575-1583 [Journal]

  29. A Systolic String Matching Algorithm for High-Speed Recognition of a Restricted Regular Set. [Citation Graph (, )][DBLP]


  30. A Parallel Multistage Metaheuristic Algorithm for VLSI Floorplanning. [Citation Graph (, )][DBLP]


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