The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Wojciech Maly: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yangdong (Steven) Deng, Wojciech Maly
    2.5D system integration: a design driven system implementation schema. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:450-455 [Conf]
  2. Aiman H. El-Maleh, Thomas E. Marchok, Janusz Rajski, Wojciech Maly
    On Test Set Preservation of Retimed Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:176-182 [Conf]
  3. Hans T. Heineken, Jitendra Khare, Wojciech Maly, Pranab K. Nag, Charles H. Ouyang, Witold A. Pleskacz
    CAD at the Design-Manufacturing Interface. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:321-326 [Conf]
  4. Wojciech Maly
    IC Design in High-Cost Nanometer-Technologies Era. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:9-14 [Conf]
  5. Wojciech Maly
    Optimal order of the VLSI IC testing sequence. [Citation Graph (0, 0)][DBLP]
    DAC, 1986, pp:560-566 [Conf]
  6. Wojciech Maly
    Realistic Fault Modeling for VLSI Testing. [Citation Graph (0, 0)][DBLP]
    DAC, 1987, pp:173-180 [Conf]
  7. Wojciech Maly
    What is Design for Manufacturability (DFM)? (Panel Abstract). [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:252- [Conf]
  8. Wojciech Maly
    Cost of Silicon Viewed from VLSI Design Perspective. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:135-142 [Conf]
  9. Hans T. Heineken, Wojciech Maly
    Performance - Manufacturability Tradeoffs in IC Design. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:563-0 [Conf]
  10. Wojciech Maly, Pranab K. Nag, Hans T. Heineken, Jitendra Khare
    Design-Manufacturing Interface: Part I - Vision. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:550-556 [Conf]
  11. Wojciech Maly, Pranab K. Nag, Charles H. Ouyang, Hans T. Heineken, Jitendra Khare, P. Simon
    Design-Manufacturing Interface: Part II - Applications. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:557-562 [Conf]
  12. Jeffrey E. Nelson, Thomas Zanon, Rao Desineni, Jason G. Brown, N. Patil, Wojciech Maly, R. D. (Shawn) Blanton
    Extraction of defect density and size distributions from wafer sort test results. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:913-918 [Conf]
  13. Witold A. Pleskacz, Wojciech Maly
    Improved Yield Model for Submicron Domain. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:2-10 [Conf]
  14. Witold A. Pleskacz, Wojciech Maly, Hans T. Heineken
    Detection of Yield Trends. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:62-68 [Conf]
  15. Hans T. Heineken, Wojciech Maly
    Interconnect yield model for manufacturability prediction in synthesis of standard cell based designs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:368-373 [Conf]
  16. Wojciech Maly, Hans T. Heineken, Jitendra Khare, Pranab K. Nag
    Design for manufacturability in submicron domain. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:690-697 [Conf]
  17. Yangdong Deng, Wojciech Maly
    Physical Design of the "2.5D" Stacked System. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:211-217 [Conf]
  18. Thomas E. Marchok, Wojciech Maly
    Modeling the Difficulty of Sequential Automatic Test Pattern Generation. [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:261-0 [Conf]
  19. Yangdong Deng, Wojciech Maly
    Interconnect characteristics of 2.5-D system integration scheme. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:171-175 [Conf]
  20. Wojciech Maly
    Moore's law and physical design of ICs. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:36- [Conf]
  21. Mariusz Niewczas, Wojciech Maly, Andrzej J. Strojwas
    A pattern matching algorithm for verification and analysis of very large IC layouts. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:129-134 [Conf]
  22. Wojciech Maly
    Quality of Design from an IC Manufacturing Perspective. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:235-236 [Conf]
  23. Ronald D. Blanton, John T. Chen, Rao Desineni, Kumar N. Dwarakanath, Wojciech Maly, Thomas J. Vogels
    Fault Tuples in Diagnosis of Deep-Submicron Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:233-241 [Conf]
  24. John T. Chen, Jitendra Khare, Ken Walker, Saghir A. Shaikh, Janusz Rajski, Wojciech Maly
    Test response compression and bitmap encoding for embedded memories in manufacturing process monitoring. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:258-267 [Conf]
  25. Anne E. Gattiker, Wojciech Maly
    Feasibility Study of Smart Substrate Multichip Modules. [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:41-49 [Conf]
  26. Anne E. Gattiker, Wojciech Maly
    Current Signatures: Application. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:156-165 [Conf]
  27. Anne E. Gattiker, Wojciech Maly
    Current signatures: application [to CMOS]. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:1168-1177 [Conf]
  28. Anne E. Gattiker, Wojciech Maly
    Toward understanding "Iddq-only" fails. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:174-183 [Conf]
  29. Jitendra Khare, Wojciech Maly
    Inductive Contamination Analysis (ICA) with SRAM Application. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:552-560 [Conf]
  30. Wojciech Maly
    Improving the Quality of Test Education. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:1119- [Conf]
  31. Wojciech Maly
    Integration of Design, Manufacturing and Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:1017- [Conf]
  32. Wojciech Maly
    New and Not-So-New Test Challenges of the Next Decade. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:11- [Conf]
  33. Wojciech Maly, F. Joel Ferguson, John Paul Shen
    Systematic Characterization of Physical Defects for Fault Analysis of MOS IC Cells. [Citation Graph (0, 0)][DBLP]
    ITC, 1984, pp:390-399 [Conf]
  34. Wojciech Maly, Anne E. Gattiker, Thomas Zanon, Thomas J. Vogels, R. D. (Shawn) Blanton, Thomas M. Storey
    Deformations of IC Structure in Test and Yield Learning. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:856-865 [Conf]
  35. Wojciech Maly, Samir B. Naik
    Process Monitoring Oriented IC Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:527-532 [Conf]
  36. Anne Meixner, Wojciech Maly
    Fault Modeling for the Testing of Mixed Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:564-572 [Conf]
  37. Phil Nigh, Wayne M. Needham, Kenneth M. Butler, Peter C. Maxwell, Robert C. Aitken, Wojciech Maly
    So What Is an Optimal Test Mix? A Discussion of the SEMATECH Methods Experiment. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:1037-1038 [Conf]
  38. Thomas M. Storey, Wojciech Maly
    CMOS Bridging Fault Detection. [Citation Graph (0, 0)][DBLP]
    ITC, 1990, pp:1123-1132 [Conf]
  39. Thomas M. Storey, Wojciech Maly, John Andrews, Myron Miske
    Stuck Fault and Current Testing Comparison Using CMOS Chip Test. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:311-318 [Conf]
  40. Thomas J. Vogels, Wojciech Maly, R. D. (Shawn) Blanton
    Progressive Bridge Identification. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:309-318 [Conf]
  41. Thomas J. Vogels, Thomas Zanon, Rao Desineni, R. D. (Shawn) Blanton, Wojciech Maly, Jason G. Brown, Jeffrey E. Nelson, Y. Fei, X. Huang, Padmini Gopalakrishnan, Mahim Mishra, V. Rovner, S. Tiwary
    Benchmarking Diagnosis Algorithms With a Diverse Set of IC Deformations. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:508-517 [Conf]
  42. Sichao Wei, Pranab K. Nag, Ronald D. Blanton, Anne E. Gattiker, Wojciech Maly
    To DFT or Not to DFT? [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:557-566 [Conf]
  43. Thomas W. Williams, R. H. Dennard, Rohit Kapur, M. Ray Mercer, Wojciech Maly
    IDDQ Test: Sensitivity Analysis of Scaling. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:786-792 [Conf]
  44. Peng Li, Pranab K. Nag, Wojciech Maly
    Cost based tradeoff analysis of standard cell designs. [Citation Graph (0, 0)][DBLP]
    SLIP, 2000, pp:129-135 [Conf]
  45. John T. Chen, Wojciech Maly, Janusz Rajski, Omar Kebichi, Jitendra Khare
    Enabling Embedded Memory Diagnosis via Test Response Compression. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:292-298 [Conf]
  46. Anne E. Gattiker, Wojciech Maly
    Current signatures [VLSI circuit testing]. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:112-117 [Conf]
  47. Jitendra Khare, Wojciech Maly, Nathan Tiday
    Fault characterization of standard cell libraries using inductive contamination. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:405-413 [Conf]
  48. Wojciech Maly
    Prospects for WSI: A Manufacturing Perspective. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1992, v:25, n:4, pp:58-65 [Journal]
  49. Wojciech Maly
    The future of IC design, testing, and manufacturing. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:4, pp:8-91 [Journal]
  50. Wojciech Maly, Derek Feltham, Anne E. Gattiker, Mark D. Hobaugh, Kenneth Backus, Michael E. Thomas
    Smart-Substrate Multichip-Module Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1994, v:11, n:2, pp:64-73 [Journal]
  51. Thomas E. Marchok, Aiman H. El-Maleh, Janusz Rajski, Wojciech Maly
    Testability Implications of Performance-Driven Logic Synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1995, v:12, n:2, pp:32-39 [Journal]
  52. Pranab K. Nag, Anne E. Gattiker, Sichao Wei, Ronald D. Blanton, Wojciech Maly
    Modeling the Economics of Testing: A DFT Perspective. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:1, pp:29-41 [Journal]
  53. Samir Naik, Frank Agricola, Wojciech Maly
    Failure Analysis of High-Density CMOS SRAMs: Using Realistic Defect Modeling and I/Sub DDQ/ Testing. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1993, v:10, n:2, pp:13-23 [Journal]
  54. Jeffrey E. Nelson, Thomas Zanon, Jason G. Brown, Osei Poku, R. D. (Shawn) Blanton, Wojciech Maly, Brady Benware, Chris Schuermyer
    Extracting Defect Density and Size Distributions from Product ICs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2006, v:23, n:5, pp:390-400 [Journal]
  55. Phil Nigh, Wojciech Maly
    Test Generation for Current Testing (CMOS ICs). [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1990, v:7, n:1, pp:26-38 [Journal]
  56. Aiman H. El-Maleh, Thomas E. Marchok, Janusz Rajski, Wojciech Maly
    Behavior and testability preservation under the retiming transformation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:5, pp:528-543 [Journal]
  57. Wojciech Maly
    Modeling of Lithography Related Yield Losses for CAD of VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1985, v:4, n:3, pp:166-177 [Journal]
  58. Wojciech Maly, Zygmunt Pizlo
    Tolerance Assignment for IC Selection Tests. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1985, v:4, n:2, pp:156-162 [Journal]
  59. Wojciech Maly, Andrzej J. Strojwas
    Statistical Simulation of the IC Manufacturing Process. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1982, v:1, n:3, pp:120-131 [Journal]
  60. Wojciech Maly, Andrzej J. Strojwas, Stephen W. Director
    VLSI Yield Prediction and Estimation: A Unified Framework. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:1, pp:114-130 [Journal]
  61. Thomas E. Marchok, Aiman H. El-Maleh, Wojciech Maly, Janusz Rajski
    A complexity analysis of sequential ATPG. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:11, pp:1409-1423 [Journal]
  62. Mariusz Niewczas, Wojciech Maly, Andrzej J. Strojwas
    An algorithm for determining repetitive patterns in very large IC layouts. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:4, pp:494-501 [Journal]
  63. Witold A. Pleskacz, Charles H. Ouyang, Wojciech Maly
    A DRC-based algorithm for extraction of critical areas for opens in large VLSI circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:2, pp:151-162 [Journal]
  64. W. Maly, Yi-Wei Lin, Malgorzata Marek-Sadowska
    OPC-Free and Minimally Irregular IC Design Style. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:954-957 [Conf]

  65. More Moore: foolish, feasible, or fundamentally different? [Citation Graph (, )][DBLP]


  66. Is there always performance overhead for regular fabric? [Citation Graph (, )][DBLP]


  67. Vertical slit transistor based integrated circuits (VeSTICs) paradigm. [Citation Graph (, )][DBLP]


  68. Transistor-level layout of high-density regular circuits. [Citation Graph (, )][DBLP]


  69. Performance study of VeSFET-based, high-density regular circuits. [Citation Graph (, )][DBLP]


Search in 0.006secs, Finished in 0.010secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002