The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Anand Raghunathan: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Sujit Dey, Anand Raghunathan, Rabindra K. Roy
    Considering Testability during High-level Design (Embedded Tutorial). [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:205-210 [Conf]
  2. Kanishka Lahiri, Sujit Dey, Debashis Panigrahi, Anand Raghunathan
    Battery-Driven System Design: A New Frontier in Low Power Design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:261-267 [Conf]
  3. Vijay Raghunathan, Mani B. Srivastava, Milos D. Ercegovac, Anand Raghunathan
    High-Level Synthesis with SIMD Units. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:407-413 [Conf]
  4. Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha
    Input Space Adaptive Embedded Software Synthesis. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:711-718 [Conf]
  5. Joel Coburn, Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar
    SECA: security-enhanced communication architecture. [Citation Graph (0, 0)][DBLP]
    CASES, 2005, pp:78-89 [Conf]
  6. Divya Arora, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
    Enhancing security through hardware-assisted run-time validation of program data properties. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2005, pp:190-195 [Conf]
  7. Kanishka Lahiri, Anand Raghunathan
    Power analysis of system-level on-chip communication architectures. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:236-241 [Conf]
  8. Kanishka Lahiri, Anand Raghunathan, Sujit Dey
    Fast system-level power profiling for battery-efficient system design. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:157-162 [Conf]
  9. Marcello Lajolo, Anand Raghunathan, Sujit Dey, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli
    A case study on modeling shared memory access effects during performance analysis of HW/SW systems. [Citation Graph (0, 0)][DBLP]
    CODES, 1998, pp:117-121 [Conf]
  10. Divya Arora, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
    Architectural support for safe software execution on embedded processors. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:106-111 [Conf]
  11. Tat Kee Tan, Anand Raghunathan, Niraj K. Jha
    An Energy-Aware Synthesis Methodology for OS-Driven Multi-Process Embedded Software. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:601-605 [Conf]
  12. Divya Arora, Anand Raghunathan, Srivaths Ravi, Murugan Sankaradass, Niraj K. Jha, Srimat T. Chakradhar
    Software architecture exploration for high-performance security processing on a multiprocessor mobile SoC. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:496-501 [Conf]
  13. Li Chen, Srivaths Ravi, Anand Raghunathan, Sujit Dey
    A scalable software-based self-test methodology for programmable processors. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:548-553 [Conf]
  14. Joel Coburn, Srivaths Ravi, Anand Raghunathan
    Power emulation: a new paradigm for power estimation. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:700-705 [Conf]
  15. Robert P. Dick, Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha
    Power analysis of embedded operating systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:312-315 [Conf]
  16. Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha
    Hierarchical Test Generation and Design for Testability of ASPPs and ASIPs. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:534-539 [Conf]
  17. Pallav Gupta, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Efficient fingerprint-based user authentication for embedded systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:244-247 [Conf]
  18. Kanishka Lahiri, Sujit Dey, Anand Raghunathan
    Communication architecture based power management for battery efficient system design. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:691-696 [Conf]
  19. Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana
    LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip Designs. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:15-20 [Conf]
  20. Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana, Sujit Dey
    Communication architecture tuners: a methodology for the design of high-performance communication architectures for systems-on-chips. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:513-518 [Conf]
  21. Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha
    Incorporating Speculative Execution into Scheduling of Control-Flow Intensive Behavioral Descriptions. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:108-113 [Conf]
  22. Ganesh Lakshminarayana, Anand Raghunathan, Kamal S. Khouri, Niraj K. Jha, Sujit Dey
    Common-Case Computation: A High-Level Technique for Power and Performance Optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:56-61 [Conf]
  23. Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
    Automated energy/performance macromodeling of embedded software. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:99-102 [Conf]
  24. Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
    Hybrid simulation for embedded software energy estimation. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:23-26 [Conf]
  25. Mihalis Psarakis, Dimitris Gizopoulos, Miltiadis Hatzimihail, Antonis M. Paschalis, Anand Raghunathan, Srivaths Ravi
    Systematic software-based self-test for pipelined processors. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:393-398 [Conf]
  26. Srivaths Ravi, Paul C. Kocher, Ruby B. Lee, Gary McGraw, Anand Raghunathan
    Security as a new dimension in embedded system design. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:753-760 [Conf]
  27. Srivaths Ravi, Anand Raghunathan, Nachiketh R. Potlapally, Murugan Sankaradass
    System design methodologies for a wireless security processing platform. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:777-782 [Conf]
  28. Anand Raghunathan, Sujit Dey, Niraj K. Jha
    Glitch Analysis and Reduction in Register Transfer Level. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:331-336 [Conf]
  29. Anand Raghunathan, Sujit Dey, Niraj K. Jha, Kazutoshi Wakabayashi
    Power Management Techniques for Control-Flow Intensive Designs. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:429-434 [Conf]
  30. Krishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey
    FLEXBUS: a high-performance system-on-chip communication architecture with a dynamically configurable topology. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:571-574 [Conf]
  31. Tat Kee Tan, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha
    High-level Software Energy Macro-modeling. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:605-610 [Conf]
  32. W. Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha
    Input Space Adaptive Design: A High-level Methodology for Energy and Performance Optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:738-743 [Conf]
  33. Najwa Aaraj, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Architectures for efficient face authentication in embedded systems. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:1-6 [Conf]
  34. Divya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Secure Embedded Processing through Hardware-Assisted Run-Time Monitoring. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:178-183 [Conf]
  35. Davide Bertozzi, Anand Raghunathan, Luca Benini, Srivaths Ravi
    Transport Protocol Optimization for Energy Efficient Wireless Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10706-10713 [Conf]
  36. Joel Coburn, Srivaths Ravi, Anand Raghunathan
    Hardware Accelerated Power Estimation. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:528-529 [Conf]
  37. Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Energy Estimation for Extensible Processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10682-10687 [Conf]
  38. Marcello Lajolo, Anand Raghunathan, Sujit Dey, Luciano Lavagno
    Efficient Power Co-Estimation Techniques for System-on-Chip Design. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:27-34 [Conf]
  39. Nachiketh R. Potlapally, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha, Ruby B. Lee
    Satisfiability-based framework for enabling side-channel attacks on cryptographic software. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:18-23 [Conf]
  40. Anand Raghunathan, Srivaths Ravi, Sunil Hattangady, Jean-Jacques Quisquater
    Securing Mobile Appliances: New Challenges for the System Designer. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10176-10183 [Conf]
  41. Krishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey
    Integrated data relocation and bus reconfiguration for adaptive system-on-chip platforms. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:728-733 [Conf]
  42. Phillip Stanley-Marbell, Kanishka Lahiri, Anand Raghunathan
    Adaptive data placement in an embedded multiprocessor thread library. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:698-699 [Conf]
  43. Tat Kee Tan, Anand Raghunathan, Niraj K. Jha
    Software Architectural Transformations: A New Approach to Low Energy Embedded Software. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11046-11051 [Conf]
  44. Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha
    Behavioral Synthesis of Fault Secure Controller?Datapaths using Aliasing Probability Analysis. [Citation Graph (0, 0)][DBLP]
    FTCS, 1996, pp:336-345 [Conf]
  45. Weidong Wang, Tat Kee Tan, Jiong Luo, Yunsi Fei, Li Shang, Keith S. Vallerio, Lin Zhong, Anand Raghunathan, Niraj K. Jha
    A comprehensive high-level synthesis system for control-flow intensive behaviors. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2003, pp:11-14 [Conf]
  46. Pranav Ashar, Subhrajit Bhattacharya, Anand Raghunathan, Akira Mukaiyama
    Verification of RTL generated from scheduled behavior in a high-level synthesis flow. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:517-524 [Conf]
  47. Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha
    A design for testability technique for RTL circuits using control/data flow extraction. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:329-336 [Conf]
  48. Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    High-level synthesis of distributed logic-memory architectures. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:564-571 [Conf]
  49. Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Synthesis of Heterogeneous Distributed Architectures for Memory-Intensive Applications. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:46-53 [Conf]
  50. Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    High-level synthesis using computation-unit integrated memories. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:783-790 [Conf]
  51. Kanishka Lahiri, Anand Raghunathan, Sujit Dey
    Efficient Exploration of the SoC Communication Architecture Design Space. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:424-430 [Conf]
  52. Kanishka Lahiri, Anand Raghunathan, Sujit Dey
    Fast performance analysis of bus-based system-on-chip communication architectures. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:566-573 [Conf]
  53. Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey
    Transforming control-flow intensive designs to facilitate power management. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:657-664 [Conf]
  54. Anand Raghunathan, Srimat T. Chakradhar
    Acceleration techniques for dynamic vector compaction. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:310-317 [Conf]
  55. Anand Raghunathan, Sujit Dey, Niraj K. Jha
    Register-transfer level estimation techniques for switching activity and power consumption. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:158-165 [Conf]
  56. Anand Raghunathan, Niraj K. Jha
    An iterative improvement algorithm for low power data path synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:597-602 [Conf]
  57. Vijay Raghunathan, Srivaths Ravi, Anand Raghunathan, Ganesh Lakshminarayana
    Transient Power Management Through High Level Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:545-552 [Conf]
  58. Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Synthesis of custom processors based on extensible platforms. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:641-648 [Conf]
  59. Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    A Scalable Application-Specific Processor Synthesis Methodology. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:283-290 [Conf]
  60. Lin Zhong, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Power estimation for cycle-accurate functional descriptions of hardware. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:668-675 [Conf]
  61. Pranav Ashar, Anand Raghunathan, Aarti Gupta, Subhrajit Bhattacharya
    Verification of Scheduling in the Presence of Loops Using Uninterpreted Symbolic Simulation. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:458-466 [Conf]
  62. Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha
    Design for hierarchical testability of RTL circuits obtained by behavioral synthesis. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:173-179 [Conf]
  63. Anand Raghunathan, Niraj K. Jha
    Behavioral Synthesis for low Power. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:318-322 [Conf]
  64. Tat Kee Tan, Anand Raghunathan, Niraj K. Jha
    Embedded Operating System Energy Analysis and Macro-Modeling. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:515-520 [Conf]
  65. Anand Raghunathan, Niraj K. Jha
    An ILP Formulation for Low Power Based on Minimizing Switched Capacitance During Data Path Allocation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:1069-1073 [Conf]
  66. Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
    Active Learning Driven Data Acquisition for Sensor Networks. [Citation Graph (0, 0)][DBLP]
    ISCC, 2006, pp:929-934 [Conf]
  67. Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Analyzing the energy consumption of security protocols. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:30-35 [Conf]
  68. Anand Raghunathan, Sujit Dey, Niraj K. Jha, Kazutoshi Wakabayashi
    Controller re-specification to minimize switching activity in controller/data path circuits. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:301-304 [Conf]
  69. Saumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey
    Considering process variations during system-level power analysis. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:342-345 [Conf]
  70. Anand Raghunathan, Nachiketh R. Potlapally, Srivaths Ravi
    Securing Wireless Data: System Architecture Challenges. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:195-200 [Conf]
  71. Nikhil Bansal, Kanishka Lahiri, Anand Raghunathan, Srimat T. Chakradhar
    Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:579-585 [Conf]
  72. Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Energy-Optimizing Source Code Transformations for OS-driven Embedded Software. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:261-266 [Conf]
  73. Kanishka Lahiri, Sujit Dey, Anand Raghunathan
    Performance Analysis of Systems with Multi-Channel Communication Architectures. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:530-537 [Conf]
  74. Kanishka Lahiri, Sujit Dey, Anand Raghunathan
    Evaluation of the Traffic-Performance Characteristics of System-on-Chip Communication Architectures. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:29-35 [Conf]
  75. Kanishka Lahiri, Anand Raghunathan, Sujit Dey, Debashis Panigrahi
    Embedded Tutorial: Battery-Driven System Design: A New Frontier in Low Power Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:261-267 [Conf]
  76. Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey
    A Power Management Methodology for High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:24-19 [Conf]
  77. Loganathan Lingappan, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha, Srimat T. Chakradhar
    Heterogeneous and Multi-Level Compression Techniques for Test Volume Reduction in Systems-on-Chip. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:65-70 [Conf]
  78. Debashis Panigrahi, Sujit Dey, Ramesh R. Rao, Kanishka Lahiri, Carla-Fabiana Chiasserini, Anand Raghunathan
    Battery Life Estimation of Mobile Embedded Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:57-63 [Conf]
  79. Nachiketh R. Potlapally, Michael S. Hsiao, Anand Raghunathan, Ganesh Lakshminarayana, Srimat T. Chakradhar
    Accurate Power Macro-modeling Techniques for Complex RTL Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:235-241 [Conf]
  80. Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Ruby B. Lee, Niraj K. Jha
    Impact of Configurability and Extensibility on IPSec Protocol Execution on Embedded Processors. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:299-304 [Conf]
  81. Anand Raghunathan, Pranav Ashar, Sharad Malik
    Test generation for cyclic combinational circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:104-109 [Conf]
  82. Anand Raghunathan, Srimat T. Chakradhar
    Dynamic test Sequence compaction for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:170-173 [Conf]
  83. Anand Raghunathan, Sujit Dey
    Low-Power Mobile Wireless Communication System Design: Protocols, Architectures, and Design Methodologies. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:9-10 [Conf]
  84. Vijay Raghunathan, Anand Raghunathan, Mani B. Srivastava, Milos D. Ercegovac
    High-Level Synthesis with SIMD Units. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:407-413 [Conf]
  85. Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar
    Embedding Security in Wireless Embedded Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:269-270 [Conf]
  86. Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar
    Efficient RTL Power Estimation for Large Designs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:431-439 [Conf]
  87. Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar
    Tamper Resistance Mechanisms for Secure, Embedded Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:605-0 [Conf]
  88. Kaushik Roy, Anand Raghunathan, Sujit Dey
    Low Power Design Methodologies for Systems-on-Chips. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:609- [Conf]
  89. Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Synthesis of Application-Specific Heterogeneous Multiprocessor Architectures Using Extensible Processors. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:551-556 [Conf]
  90. Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Hybrid Custom Instruction and Co-Processor Synthesis Methodology for Extensible Processors. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:473-476 [Conf]
  91. Weidong Wang, Niraj K. Jha, Anand Raghunathan, Sujit Dey
    High-level Synthesis of Multi-process Behavioral Descriptions. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:467-473 [Conf]
  92. Weidong Wang, Anand Raghunathan, Niraj K. Jha
    Profiling Driven Computation Reuse: An Embedded Software Synthesis Technique for Energy and Performance Optimization. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:267-0 [Conf]
  93. Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha
    Input Space Adaptive Embedded Software Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:711-718 [Conf]
  94. Nikhil Bansal, Kanishka Lahiri, Anand Raghunathan
    Automatic Power Modeling of Infrastructure IP for System-on-Chip Power Analysis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:513-520 [Conf]
  95. J. Borel, Anand Raghunathan, Jim Sproch, Michael Howells, Janusz Rajski
    Innovations in Test Automation. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:43-46 [Conf]
  96. Kanishka Lahiri, Sujit Dey, Anand Raghunathan
    Communication-Based Power Management. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:4, pp:118-130 [Journal]
  97. Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha
    Behavioral Synthesis of Fault Secure Controller/Datapaths Based on Aliasing Probability Analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2000, v:49, n:9, pp:865-885 [Journal]
  98. Srimat T. Chakradhar, Anand Raghunathan
    Bottleneck removal algorithm for dynamic compaction in sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:10, pp:1157-1172 [Journal]
  99. Sujit Dey, Anand Raghunathan, Niraj K. Jha, Kazutoshi Wakabayashi
    Controller-based power management for control-flow intensive designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:10, pp:1496-1508 [Journal]
  100. Robert P. Dick, Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha
    Analysis of power dissipation in embedded systems using real-time operating systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:5, pp:615-627 [Journal]
  101. Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    A hybrid energy-estimation technique for extensible processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:5, pp:652-664 [Journal]
  102. Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha
    Design for hierarchical testability of RTL circuits obtained by behavioral synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:9, pp:1001-1014 [Journal]
  103. Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha
    A design-for-testability technique for register-transfer level circuits using control/data flow extraction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:8, pp:706-723 [Journal]
  104. Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha
    Hierarchical test generation and design for testability methods for ASPPs and ASIPs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:3, pp:357-370 [Journal]
  105. Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Generation of distributed logic-memory architectures through high-level synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:11, pp:1694-1711 [Journal]
  106. Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Use of Computation-Unit Integrated Memories in High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:1969-1989 [Journal]
  107. Kanishka Lahiri, Anand Raghunathan, Sujit Dey
    System-level performance analysis for designing on-chipcommunication architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:6, pp:768-783 [Journal]
  108. Kanishka Lahiri, Anand Raghunathan, Sujit Dey
    Efficient power profiling for battery-driven embedded system design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:6, pp:919-932 [Journal]
  109. Kanishka Lahiri, Anand Raghunathan, Sujit Dey
    Design space exploration for optimizing on-chip communication architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:6, pp:952-961 [Journal]
  110. Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana, Sujit Dey
    Design of high-performance system-on-chips using communication architecture tuners. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:5, pp:620-636 [Journal]
  111. Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha
    Incorporating speculative execution into scheduling ofcontrol-flow-intensive designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:3, pp:308-324 [Journal]
  112. Ganesh Lakshminarayana, Anand Raghunathan, Kamal S. Khouri, Niraj K. Jha, Sujit Dey
    Common-case computation: a high-level energy and performance optimization technique. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:1, pp:33-49 [Journal]
  113. Loganathan Lingappan, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha, Srimat T. Chakradhar
    Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2193-2206 [Journal]
  114. Anand Raghunathan, Pranav Ashar, Sharad Malik
    Test generation for cyclic combinational circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:11, pp:1408-1414 [Journal]
  115. Anand Raghunathan, Sujit Dey, Niraj K. Jha
    Register transfer level power optimization with emphasis on glitch analysis and reduction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:8, pp:1114-1131 [Journal]
  116. Anand Raghunathan, Niraj K. Jha
    SCALP: an iterative-improvement-based low-power data path synthesis system. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:11, pp:1260-1277 [Journal]
  117. Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Custom-instruction synthesis for extensible-processor platforms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:2, pp:216-228 [Journal]
  118. Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Application-specific heterogeneous multiprocessor synthesis using extensible processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:9, pp:1589-1602 [Journal]
  119. Tat Kee Tan, Anand Raghunathan, Niraj K. Jha
    A simulation framework for energy-consumption analysis of OS-driven embedded applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:9, pp:1284-1294 [Journal]
  120. Tat Kee Tan, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha
    High-level energy macromodeling of embedded software. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:9, pp:1037-1050 [Journal]
  121. Weidong Wang, Anand Raghunathan, Niraj K. Jha, Sujit Dey
    Resource budgeting for Multiprocess High-level synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:7, pp:1010-1019 [Journal]
  122. Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha
    Input space-adaptive optimization for embedded-software synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:11, pp:1677-1693 [Journal]
  123. Lin Zhong, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    RTL-Aware Cycle-Accurate Functional Power Estimation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2103-2117 [Journal]
  124. Tat Kee Tan, Anand Raghunathan, Niraj K. Jha
    Energy macromodeling of embedded operating systems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2005, v:4, n:1, pp:231-254 [Journal]
  125. Srivaths Ravi, Anand Raghunathan, Paul C. Kocher, Sunil Hattangady
    Security in embedded systems: Design challenges. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2004, v:3, n:3, pp:461-491 [Journal]
  126. Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    A Study of the Energy Consumption Characteristics of Cryptographic Algorithms and Security Protocols. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Mob. Comput., 2006, v:5, n:2, pp:128-143 [Journal]
  127. Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha
    Input space adaptive design: a high-level methodology for optimizing energy and performance. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:6, pp:590-602 [Journal]
  128. Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana
    The LOTTERYBUS on-chip communication architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:6, pp:596-608 [Journal]
  129. Mohammad Ali Ghodrat, Kanishka Lahiri, Anand Raghunathan
    Accelerating System-on-Chip Power Analysis Using Hybrid Power Estimation. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:883-886 [Conf]
  130. Saumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey
    System-on-Chip Power Management Considering Leakage Power Variations. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:877-882 [Conf]
  131. Najwa Aaraj, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
    Energy and execution time analysis of a software-based trusted platform module. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1128-1133 [Conf]
  132. Joel Coburn, Srivaths Ravi, Anand Raghunathan
    Hardware Accelerated Power Estimation [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  133. Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    A Scalable Synthesis Methodology for Application-Specific Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:11, pp:1175-1188 [Journal]
  134. Divya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Hardware-Assisted Run-Time Monitoring for Secure Program Execution on Embedded Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:12, pp:1295-1308 [Journal]
  135. Divya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Architectural Support for Run-Time Validation of Program Data Properties. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:5, pp:546-559 [Journal]
  136. Najwa Aaraj, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Hybrid Architectures for Efficient and Secure Face Authentication in Embedded Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:3, pp:296-308 [Journal]
  137. Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Ruby B. Lee, Niraj K. Jha
    Configuration and Extension of Embedded Processors to Optimize IPSec Protocol Execution. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:5, pp:605-609 [Journal]
  138. Divya Arora, Anand Raghunathan, Srivaths Ravi, Murugan Sankaradass, Niraj K. Jha, Srimat T. Chakradhar
    Exploring Software Partitions for Fast Security Processing on a Multiprocessor Mobile SoC. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:6, pp:699-710 [Journal]
  139. Nachiketh R. Potlapally, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha, Ruby B. Lee
    Aiding Side-Channel Attacks on Cryptographic Software With Satisfiability-Based Analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:4, pp:465-470 [Journal]
  140. Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Generation of Heterogeneous Distributed Architectures for Memory-Intensive Applications Through High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:11, pp:1191-1204 [Journal]
  141. Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey
    Power management in high-level synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:1, pp:7-15 [Journal]
  142. Marcello Lajolo, Anand Raghunathan, Sujit Dey, Luciano Lavagno
    Cosimulation-based power estimation for system-on-chip design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:3, pp:253-266 [Journal]
  143. Anand Raghunathan, Sujit Dey, Niraj K. Jha
    High-level macro-modeling and estimation techniques for switching activity and power consumption. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:4, pp:538-557 [Journal]

  144. A Secure User Interface for Web Applications Running Under an Untrusted Operating System. [Citation Graph (, )][DBLP]


  145. Best-effort semantic document search on GPUs. [Citation Graph (, )][DBLP]


  146. Best-effort computing: re-thinking parallel software and hardware. [Citation Graph (, )][DBLP]


  147. Scalable effort hardware design: exploiting algorithmic resilience for energy efficiency. [Citation Graph (, )][DBLP]


  148. Efficient Software Architecture for IPSec Acceleration Using a Programmable Security Processor. [Citation Graph (, )][DBLP]


  149. An architecture for secure software defined radio. [Citation Graph (, )][DBLP]


  150. Dynamic Binary Instrumentation-Based Framework for Malware Defense. [Citation Graph (, )][DBLP]


  151. Bottleneck removal algorithm for dynamic compaction and test cycles reduction. [Citation Graph (, )][DBLP]


  152. A framework for efficient and scalable execution of domain-specific templates on GPUs. [Citation Graph (, )][DBLP]


  153. Best-effort parallel execution framework for Recognition and mining applications. [Citation Graph (, )][DBLP]


  154. Coping with Variations through System-Level Design. [Citation Graph (, )][DBLP]


  155. Integrated Systems in the More-than-Moore Era: Designing Low-Cost Energy-Efficient Systems Using Heterogeneous Components. [Citation Graph (, )][DBLP]


  156. Guest Editors' Introduction: Security and Trust in Embedded-Systems Design. [Citation Graph (, )][DBLP]


Search in 0.022secs, Finished in 0.030secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002