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Nagu R. Dhanwada: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Nagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri
    Automatic Constraint Transformation with Integrated Parameter Space Exploration in Analog System Synthesis. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:153-156 [Conf]
  2. Nagu R. Dhanwada, Ing-Chao Lin, Vijay Narayanan
    A power estimation methodology for systemC transaction level models. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2005, pp:142-147 [Conf]
  3. Reinaldo A. Bergamaschi, Youngsoo Shin, Nagu R. Dhanwada, Subhrajit Bhattacharya, William E. Dougherty, Indira Nair, John A. Darringer, Sarala Paliwal
    SEAS: a system for early analysis of SoCs. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2003, pp:150-155 [Conf]
  4. Alex Doboli, Adrián Núñez-Aldana, Nagu R. Dhanwada, Sree Ganesan, Ranga Vemuri
    Behavioral Synthesis of Analog Systems Using Two-layered Design Space Exploration. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:951-957 [Conf]
  5. Nagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri
    Hierarchical Constraint Transformation Using Directed Interval Search for Analog System Synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:328-0 [Conf]
  6. Shyam Ramji, Nagu R. Dhanwada
    Design topology aware physical metrics for placement analysis. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2003, pp:186-191 [Conf]
  7. Wei-Lun Hung, Greg M. Link, Yuan Xie, Narayanan Vijaykrishnan, Nagu R. Dhanwad, John Conner
    Temperature-Aware Voltage Islands Architecting in System-on-Chip Design. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:689-696 [Conf]
  8. Nagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri
    A genetic approach to simultaneous parameter space exploration and constraint transformation in analog synthesis. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 1999, pp:362-365 [Conf]
  9. Jingcao Hu, Youngsoo Shin, Nagu R. Dhanwada, Radu Marculescu
    Architecting voltage islands in core-based system-on-a-chip designs. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:180-185 [Conf]
  10. I.-C. Lin, S. Srinivasan, Narayanan Vijaykrishnan, N. Dhanwada
    Transaction Level Error Susceptibility Model for Bus Based SoC Architectures. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:775-780 [Conf]
  11. Nagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri
    Component Characterization and Constraint Transformation Based on Directed Intervals for Analog Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:589-596 [Conf]
  12. Nagu R. Dhanwada, Ranga Vemuri
    Constraint Allocation in Analog System Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:253-258 [Conf]
  13. Nagu R. Dhanwada, Alex Doboli, Adrián Núñez-Aldana, Ranga Vemuri
    Hierarchical constraint transformation based on genetic optimization for analog system synthesis. [Citation Graph (0, 0)][DBLP]
    Integration, 2006, v:39, n:3, pp:267-290 [Journal]
  14. Alex Doboli, Nagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri
    A two-layer library-based approach to synthesis of analog systems from VHDL-AMS specifications. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2004, v:9, n:2, pp:238-271 [Journal]

  15. Exploring power management in multi-core systems. [Citation Graph (, )][DBLP]


  16. Performance modeling for early analysis of multi-core systems. [Citation Graph (, )][DBLP]


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