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Yu-Liang Wu: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jin Ding, Yu-Liang Wu
    On the Testing Quality of Random and Pseudo-random Sequences for Permanent and Intermittent Faults. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:311-314 [Conf]
  2. Hongbing Fan, Jiping Liu, Yu-Liang Wu
    Combinatorial routing analysis and design of universal switch blocks. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:641-644 [Conf]
  3. Hongbing Fan, Yu-Liang Wu
    Crossbar based design schemes for switch boxes and programmable interconnection networks. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:910-915 [Conf]
  4. Wangning Long, Yu-Liang Wu, Jinian Bian
    IBAW: an implication-tree based alternative-wiring logic transformation algorithm. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:415-422 [Conf]
  5. Yu-Liang Wu, Malgorzata Marek-Sadowska
    Routing on regular segmented 2-D FPGAs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  6. Jiaofeng Pan, Yu-Liang Wu, C. K. Wong
    On the Optimal Sub-routing Structures of 2-D FPGA Greedy Routing Architectures. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:535-540 [Conf]
  7. Chin Ngai Sze, Yu-Liang Wu
    Improved alternative wiring scheme applying dominator relationship. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:473-478 [Conf]
  8. Yu-Liang Wu, Xiao-Long Yuan, David Ihsin Cheng
    Circuit partitioning with coupled logic restructuring techniques. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:655-660 [Conf]
  9. Dong Xiang, Ming-Jing Chen, Kai-Wei Li, Yu-Liang Wu
    Scan-Based BIST Using an Improved Scan Forest Architecture. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:88-93 [Conf]
  10. Hongbing Fan, Jiping Liu, Yu-Liang Wu, Chak-Chung Cheung
    On Optimum Switch Box Designs for 2-D FPGAs. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:203-208 [Conf]
  11. Yu-Liang Wu, Malgorzata Marek-Sadowska
    Orthogonal Greedy Coupling - A New Optimization Approach to 2-D FPGA Routing. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:568-573 [Conf]
  12. Dong Xiang, Shan Gu, Jia-Guang Sun, Yu-Liang Wu
    A cost-effective scan architecture for scan testing with non-scan test power and test application cost. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:744-747 [Conf]
  13. Chak-Chung Cheung, Yu-Liang Wu, David Ihsin Cheng
    Further improve circuit partitioning using GBAW logic perturbation techniques. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:233-239 [Conf]
  14. Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone
    Design and Analysis of Self-Repairable MEMS Accelerometer. [Citation Graph (0, 0)][DBLP]
    DFT, 2005, pp:21-32 [Conf]
  15. Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone
    Reliability Analysis of Self-Repairable MEMS Accelerometer. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:236-244 [Conf]
  16. Yu-Liang Wu, Malgorzata Marek-Sadowska
    An Efficient Router for 2-D Field Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:412-416 [Conf]
  17. Hongbing Fan, Jiping Liu, Yu-Liang Wu, Chak-Chung Cheung
    On Optimum Designs of Universal Switch Blocks. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:142-151 [Conf]
  18. Hongbing Fan, Yu-Liang Wu, Chak-Chung Cheung, Jiping Liu
    On Optimal Irregular Switch Box Designs. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:189-199 [Conf]
  19. Hongbing Fan, Jiping Liu, Yu-Liang Wu
    General Models for Optimum Arbitrary-Dimension FPGA Switch Box Designs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:93-98 [Conf]
  20. Yu-Liang Wu, Douglas Chang
    On the NP-completeness of regular 2-D FPGA routing architectures and a novel solution. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:362-366 [Conf]
  21. Wai-Chung Tang, Wing-Hang Lo, Yu-Liang Wu, Shih-Chieh Chang
    FPGA technology mapping optimization by rewiring algorithms. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5653-5656 [Conf]
  22. Wen-Ben Jone, Jiann-Chyi Rau, Shih-Chieh Chang, Yu-Liang Wu
    A tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:322-330 [Conf]
  23. Yu-Liang Wu, Chi-Kong Chan
    On Improved Least Flexibility First Heuristics Superior for Packing and Stock Cutting Problems. [Citation Graph (0, 0)][DBLP]
    SAGA, 2005, pp:70-81 [Conf]
  24. Yu-Liang Wu, Wangning Long, Hongbing Fan
    A Fast Graph-Based Alternative Wiring Scheme for Boolean Networks. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:268-273 [Conf]
  25. Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone
    A Dual-Mode Built-In Self-Test Technique for Capacitive MEMS Devices. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:148-153 [Conf]
  26. Hongbing Fan, Yu-Liang Wu, C. K. Wong
    On Fixed Edges and Edge-Reconstruction of Series-Parallel Networks. [Citation Graph (0, 0)][DBLP]
    Graphs and Combinatorics, 2001, v:17, n:2, pp:213-225 [Journal]
  27. Jiaofeng Pan, Yu-Liang Wu, C. K. Wong, Guiying Yan
    On the optimal four-way switch box routing structures of FPGA greedy routing architectures1. [Citation Graph (0, 0)][DBLP]
    Integration, 1998, v:25, n:2, pp:137-159 [Journal]
  28. Hongbing Fan, Jiping Liu, Yu-Liang Wu
    General Models and a Reduction Design Technique for FPGA Switch Box Designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:1, pp:21-30 [Journal]
  29. Hongbing Fan, Yu-Liang Wu, Yao-Wen Chang
    Comment on Generic Universal Switch Blocks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2002, v:51, n:1, pp:93-96 [Journal]
  30. Hongbing Fan, Yu-Liang Wu, Ray Chak-Chung Cheung, Jiping Liu
    Decomposition Design Theory and Methodology for Arbitrary-Shaped Switch Boxes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:4, pp:373-384 [Journal]
  31. Yu-Liang Wu, Hongbing Fan, Malgorzata Marek-Sadowska, C. K. Wong
    OBDD Minimization Based on Two-Level Representation of Boolean Functions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2000, v:49, n:12, pp:1371-1379 [Journal]
  32. Hongbing Fan, Jiping Liu, Yu-Liang Wu, Chak-Chung Cheung
    On optimal hyperuniversal and rearrangeable switch box designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:12, pp:1637-1649 [Journal]
  33. Yu-Liang Wu, Malgorzata Marek-Sadowska
    Routing for array-type FPGA's. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:5, pp:506-518 [Journal]
  34. Yu-Liang Wu, Shuji Tsukiyama, Malgorzata Marek-Sadowska
    Graph based analysis of 2-D FPGA routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:1, pp:33-44 [Journal]
  35. Hongbing Fan, Jiping Liu, Yu-Liang Wu, C. K. Wong
    Reduction design for generic universal switch blocks. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:4, pp:526-546 [Journal]
  36. Yu-Liang Wu, Wenqi Huang, Siu-Chung Lau, C. K. Wong, Gilbert H. Young
    An effective quasi-human based heuristic for solving the rectangle packing problem. [Citation Graph (0, 0)][DBLP]
    European Journal of Operational Research, 2002, v:141, n:2, pp:341-358 [Journal]
  37. Catherine L. Zhou, Wai-Chung Tang, Wing-Hang Lo, Yu-Liang Wu
    How Much Can Logic Perturbation Help from Netlist to Final Routing for FPGAs. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:922-927 [Conf]
  38. Wai-Chung Tang, Wing-Hang Lo, Yu-Liang Wu
    Further Improve Excellent Graph-Based FPGA Technology Mapping by Rewiring. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1049-1052 [Conf]
  39. Hongbing Fan, Jiping Liu, Yu-Liang Wu, Chak-Chung Cheung
    The exact channel density and compound design for generic universal switch blocks. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:2, pp:- [Journal]
  40. Yu-Liang Wu, Chak-Chung Cheung, David Ihsin Cheng, Hongbing Fan
    Further improve circuit partitioning using GBAW logic perturbation techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:3, pp:451-460 [Journal]

  41. ECR: a low complexity generalized error cancellation rewiring scheme. [Citation Graph (, )][DBLP]


  42. Material Fatigue and Reliability of MEMS Accelerometers. [Citation Graph (, )][DBLP]


  43. A Quantitative Study of the Routing Architecture Exploring Routing Locality Property for Better Performance and Routability. [Citation Graph (, )][DBLP]


  44. Interconnection Graph Problem. [Citation Graph (, )][DBLP]


  45. Customized Reconfigurable Interconnection Networks for multiple application SOCS. [Citation Graph (, )][DBLP]


  46. Logic synthesis for low power using clock gating and rewiring. [Citation Graph (, )][DBLP]


  47. Design Automation for Reconfigurable Interconnection Networks. [Citation Graph (, )][DBLP]


  48. Algorithms and Implementation for Interconnection Graph Problem. [Citation Graph (, )][DBLP]


  49. A New Approach for Rearrangeable Multicast Switching Networks. [Citation Graph (, )][DBLP]


  50. Control Circuitry for Self-Repairable MEMS Accelerometers. [Citation Graph (, )][DBLP]


  51. A Less Flexibility First Based Algorithm for the Container Loading Problem. [Citation Graph (, )][DBLP]


  52. The Vertex Linear Arboricity of Claw-Free Graphs with Small Degree. [Citation Graph (, )][DBLP]


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