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Yuvraj Singh Dhillon: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]
Publications of Author
- Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh
Low-power domino circuits using NMOS pull-up on off-critical paths. [Citation Graph (0, 0)][DBLP]
ASP-DAC, 2005, pp:533-538 [Conf] - Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee
Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits. [Citation Graph (0, 0)][DBLP]
DATE, 2005, pp:288-293 [Conf] - Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Hsien-Hsin Sean Lee
Algorithm for Achieving Minimum Energy Consumption in CMOS Circuits Using Multiple Supply and Threshold Voltages at the Module Level. [Citation Graph (0, 0)][DBLP]
ICCAD, 2003, pp:693-700 [Conf] - Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh
Sizing CMOS Circuits for Increased Transient Error Tolerance. [Citation Graph (0, 0)][DBLP]
IOLTS, 2004, pp:11-16 [Conf] - Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Cecilia Metra
Load and Logic Co-Optimization for Design of Soft-Error Resistant Nanometer CMOS Circuits. [Citation Graph (0, 0)][DBLP]
IOLTS, 2005, pp:35-40 [Conf] - Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Kyu-won Choi, Abhijit Chatterjee
An O(N)Supply Voltage Assignment Algorithm for Low-Energy Serially Connected CMOS Modules and a Heuristic Extension to Acyclic Data Flow Graphs. [Citation Graph (0, 0)][DBLP]
ISVLSI, 2003, pp:173-182 [Conf] - Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh
Low-power dual Vth pseudo dual Vdd domino circuits. [Citation Graph (0, 0)][DBLP]
SBCCI, 2004, pp:273-277 [Conf] - Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh
Level-Shifter Free Design of Low Power Dual Supply Voltage CMOS Circuits Using Dual Threshold Voltages. [Citation Graph (0, 0)][DBLP]
VLSI Design, 2005, pp:159-164 [Conf] - Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh
Design of Adaptive Nanometer Digital Systems for Effective Control of Soft Error Tolerance. [Citation Graph (0, 0)][DBLP]
VTS, 2005, pp:298-303 [Conf] - Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh
Analysis and Optimization of Nanometer CMOS Circuits for Soft-Error Tolerance. [Citation Graph (0, 0)][DBLP]
IEEE Trans. VLSI Syst., 2006, v:14, n:5, pp:514-524 [Journal] - Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh
Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages. [Citation Graph (0, 0)][DBLP]
IEEE Trans. VLSI Syst., 2005, v:13, n:9, pp:1103-1107 [Journal] - Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee
Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits [Citation Graph (0, 0)][DBLP]
CoRR, 2007, v:0, n:, pp:- [Journal] - Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh
Pseudo Dual Supply Voltage Domino Logic Design. [Citation Graph (0, 0)][DBLP]
J. Low Power Electronics, 2005, v:1, n:2, pp:145-152 [Journal] - Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee
Delay-Assignment-Variation Based Optimization of Digital CMOS Circuits for Low Power Consumption. [Citation Graph (0, 0)][DBLP]
J. Low Power Electronics, 2007, v:3, n:1, pp:78-95 [Journal]
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