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Adit D. Singh: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh
    Low-power domino circuits using NMOS pull-up on off-critical paths. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:533-538 [Conf]
  2. Adit D. Singh
    T2: Statistical Methods for VLSI Test and Burn-in Optimization. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:- [Conf]
  3. Xiangdong Xuan, Abhijit Chatterjee, Adit D. Singh, Namsoo P. Kim, Mark T. Chisa
    IC Reliability Simulator ARET and Its Application in Design-for-Reliability. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:18-23 [Conf]
  4. Haihua Yan, Adit D. Singh
    Reduce Yield Loss in Delay Defect Detection in Slack Interval. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:372-377 [Conf]
  5. Haihua Yan, Adit D. Singh, Gefu Xu
    Delay Defect Characterization Using Low Voltage Test. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:8-13 [Conf]
  6. Thomas S. Barnett, Adit D. Singh, Victor P. Nelson
    Yield-Reliability Modeling for Fault Tolerant Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:29-38 [Conf]
  7. Christopher G. Knight, Adit D. Singh, Victor P. Nelson
    An IDDQ Sensor for Concurrent Timing Error Detection. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:281-289 [Conf]
  8. Adit D. Singh, David R. Lakin II, Gaurav Sinha, Phil Nigh
    Binning for IC Quality: Experimental Studies on the SEMATECH Data. [Citation Graph (0, 0)][DBLP]
    DFT, 1998, pp:4-10 [Conf]
  9. Jae Young Lee, Hee Yong Youn, Adit D. Singh
    Adaptive Voting for Faulty (VFF) Node Scheme for Distributed Self-Diagnosis. [Citation Graph (0, 0)][DBLP]
    FTCS, 1993, pp:480-489 [Conf]
  10. Adit D. Singh, C. Mani Krishna
    Chip Test Optimization Using Defect Clustering Information. [Citation Graph (0, 0)][DBLP]
    FTCS, 1992, pp:366-373 [Conf]
  11. Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh, Vivek De
    A Dual-Vt Layout Approach for Statistical Leakage Variability Minimization in Nanometer CMOS. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:567-573 [Conf]
  12. Hee Yong Youn, Adit D. Singh
    Near Optimal Embedding of Binary Tree Architecture in VLSI. [Citation Graph (0, 0)][DBLP]
    ICDCS, 1988, pp:86-93 [Conf]
  13. Hee Yong Youn, Adit D. Singh
    On Area Efficient and Fault Tolerant Tree Embedding In VLSI. [Citation Graph (0, 0)][DBLP]
    ICPP, 1987, pp:170-177 [Conf]
  14. Hee Yong Youn, Adit D. Singh
    A Highly Efficient Design for Reconfiguring the Processor Array in VLSI. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1988, pp:375-382 [Conf]
  15. Hee Yong Youn, Adit D. Singh
    A Near Optimal Adaptive Row Modular Design for Efficiently Reconfiguring the Processor Array in VLSI. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1989, pp:261-265 [Conf]
  16. Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh
    Sizing CMOS Circuits for Increased Transient Error Tolerance. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:11-16 [Conf]
  17. Adit D. Singh
    Integrating Yield, Test and Reliability: "Statistical Models with Applications to Test and Burn-in Optimization". [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:7- [Conf]
  18. Haihua Yan, Gefu Xu, Adit D. Singh
    Low Voltage Test in Place of Fast Clock in DDSI Delay Test. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:316-320 [Conf]
  19. Thomas S. Barnett, Matt Grady, Kathleen G. Purdy, Adit D. Singh
    Redundancy Implications for Early-Life Reliability: Experimental Verification of an Integrated Yield-Reliability Model. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:693-699 [Conf]
  20. Thomas S. Barnett, Adit D. Singh
    Relating Yield Models to Burn-In Fall-Out in Time. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:77-84 [Conf]
  21. Thomas S. Barnett, Adit D. Singh, Victor P. Nelson
    Estimating burn-in fall-out for redundant memory. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:340-347 [Conf]
  22. David R. Lakin II, Adit D. Singh
    Exploiting defect clustering to screen bare die for infant mortality failures: an experimental study. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:23-30 [Conf]
  23. Adit D. Singh
    Should Nanometer Circuits be Periodically Tested in the Field?. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:1280- [Conf]
  24. Adit D. Singh, C. Mani Krishna
    On Optimizing Wafer-Probe Testing for Product Quality Using Die-Yield Prediction. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:228-237 [Conf]
  25. Adit D. Singh, Phil Nigh, C. Mani Krishna
    Screening for Known Good Die (KGD) Based on Defect Clustering: An Experimental Study. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:362-369 [Conf]
  26. Adit D. Singh, Haroon Rasheed, Walter W. Weber
    IDDQ Testing of CMOS Opens: An Experimental Study. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:479-489 [Conf]
  27. Adit D. Singh, Egor S. Sogomonyan, Michael Gössel, Markus Seuring
    Testability evaluation of sequential designs incorporating the multi-mode scannable memory element. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:286-293 [Conf]
  28. Haihua Yan, Adit D. Singh
    Experiments in Detecting Delay Faults using Multiple Higher Frequency Clocks and Results from Neighboring Die. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:105-111 [Conf]
  29. Haihua Yan, Adit D. Singh
    Evaluating the Effectiveness of Detecting Delay Defects in the Slack Interval: A Simulation Study. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:242-251 [Conf]
  30. Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh
    Low-power dual Vth pseudo dual Vdd domino circuits. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:273-277 [Conf]
  31. Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh, Vivek De, T. M. Mak
    Statistical Estimation of Correlated Leakage Power Variation and Its Application to Leakage-Aware Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:606-612 [Conf]
  32. Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh
    Level-Shifter Free Design of Low Power Dual Supply Voltage CMOS Circuits Using Dual Threshold Voltages. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:159-164 [Conf]
  33. Jason P. Hurst, Adit D. Singh
    A differential built-in current sensor design for high speed IDDQ testing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:419-423 [Conf]
  34. Gefu Xu, Adit D. Singh
    Delay Test Scan Flip-Flop: DFT for High Coverage Delay Testing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:763-768 [Conf]
  35. Haihua Yan, Adit D. Singh
    A Delay Test to Differentiate Resistive Interconnect Faults from Weak Transistor Defects. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:47-52 [Conf]
  36. Maryam Ashouei, Muhammad M. Nisar, Abhijit Chatterjee, Adit D. Singh, Abdulkadir Utku Diril
    Probabilistic Self-Adaptation of Nanoscale CMOS Circuits: Yield Maximization under Increased Intra-Die Variations. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:711-716 [Conf]
  37. Thomas S. Barnett, Adit D. Singh, Matt Grady, Kathleen G. Purdy
    Yield-Reliability Modeling: Experimental Verification and Application to Burn-In Reduction. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:75-80 [Conf]
  38. Thomas S. Barnett, Adit D. Singh, Victor P. Nelson
    Burn-In Failures and Local Region Yield: An Integrated Yield-Reliability Model. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:326-332 [Conf]
  39. Michael Gössel, Egor S. Sogomonyan, Adit D. Singh
    Scan-Path with Directly Duplicated and Inverted Duplicated Registers. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:47-52 [Conf]
  40. Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh
    Design of Adaptive Nanometer Digital Systems for Effective Control of Soft Error Tolerance. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:298-303 [Conf]
  41. Adit D. Singh, Gefu Xu
    Output Hazard-Free Transition Tests for Silicon Calibrated Scan Based Delay Testing. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:349-357 [Conf]
  42. Egor S. Sogomonyan, A. A. Morosov, Jan Rzeha, Michael Gössel, Adit D. Singh
    Early Error Detection in Systems-on-Chip for Fault-Tolerance and At-Speed Debugging. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:184-189 [Conf]
  43. Egor S. Sogomonyan, Adit D. Singh, Michael Gössel
    A Multi-Mode Scannable Memory Element for High Test Application Efficiency and Delay Testing. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:324-331 [Conf]
  44. Walter W. Weber, Adit D. Singh
    An experimental evaluation of the differential BICS for I/sub DDQ/ testing. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:472-485 [Conf]
  45. Israel Koren, Adit D. Singh
    Fault Tolerance in VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1990, v:23, n:7, pp:73-83 [Journal]
  46. Adit D. Singh, Singaravel Murugesan
    Fault-Tolerant Systems - Guest Editors' Introduction to the Special Issue. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1990, v:23, n:7, pp:15-17 [Journal]
  47. Thomas S. Barnett, Matt Grady, Kathleen G. Purdy, Adit D. Singh
    Combining Negative Binomial and Weibull Distributions for Yield and Reliability Prediction. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2006, v:23, n:2, pp:110-116 [Journal]
  48. Jae Young Lee, Hee Yong Youn, Adit D. Singh
    Adaptive Unanimous Voting (UV) Scheme for Distributed Self-Diagnosis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:5, pp:730-735 [Journal]
  49. Adit D. Singh
    Interstitial Redundancy: An Area Efficient Fault Tolerance Scheme for Large Area VLSI Processor Arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1988, v:37, n:11, pp:1398-1410 [Journal]
  50. Adit D. Singh, C. Mani Krishna
    On the Effect of Defect Clustering on Test Transparency and IC Test Optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:6, pp:753-757 [Journal]
  51. Adit D. Singh, Hee Yong Youn
    A Modular Fault-Tolerant Binary Tree Architecture with Short Links. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1991, v:40, n:7, pp:882-890 [Journal]
  52. Hee Yong Youn, Adit D. Singh
    On Implementing Large Binary Tree Architectures in VLSI and WSI. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1989, v:38, n:4, pp:526-537 [Journal]
  53. Adit D. Singh, C. Mani Krishna
    On optimizing VLSI testing for product quality using die-yield prediction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:5, pp:695-709 [Journal]
  54. Adit D. Singh, Markus Seuring, Michael Gössel, Egor S. Sogomonyan
    Multimode scan: Test per clock BIST for IP cores. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2003, v:8, n:4, pp:491-505 [Journal]
  55. Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh
    Analysis and Optimization of Nanometer CMOS Circuits for Soft-Error Tolerance. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:5, pp:514-524 [Journal]
  56. Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh
    Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:9, pp:1103-1107 [Journal]
  57. Gefu Xu, Adit D. Singh
    Low Cost Launch-on-Shift Delay Test with Slow Scan Enable. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:9-14 [Conf]
  58. Thomas S. Barnett, Adit D. Singh, Victor P. Nelson
    Extending integrated-circuit yield-models to estimate early-life reliability. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Reliability, 2003, v:52, n:3, pp:296-300 [Journal]
  59. Haihua Yan, Adit D. Singh
    A New Delay Test Based on Delay Defect Detection Within Slack Intervals (DDSI). [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:11, pp:1216-1226 [Journal]
  60. Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh
    Pseudo Dual Supply Voltage Domino Logic Design. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2005, v:1, n:2, pp:145-152 [Journal]
  61. Xiangdong Xuan, Adit D. Singh, Abhijit Chatterjee
    Lifetime Prediction and Design-for-Reliability of IC Interconnections with Electromigration Induced Degradation in the Presence of Manufacturing Defects. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2006, v:22, n:4-6, pp:471-482 [Journal]
  62. Bashir M. Al-Hashimi, Dimitris Gizopoulos, Manoj Sachdev, Adit D. Singh
    New JETTA Editors, 2006. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2006, v:22, n:1, pp:9-10 [Journal]

  63. Leveraging Partially Enhanced Scan for Improved Observability in Delay Fault Testing. [Citation Graph (, )][DBLP]


  64. A Defect Tolerant and Performance Tunable Gate Architecture for End-of-Roadmap CMOS. [Citation Graph (, )][DBLP]


  65. Panel: Realistic low power design: Let errors occur and correct them later or mitigate errors via design guardbanding and process control?. [Citation Graph (, )][DBLP]


  66. Reconfiguring CMOS as Pseudo N/PMOS for Defect Tolerance in Nano-Scale CMOS. [Citation Graph (, )][DBLP]


  67. Scan Delay Testing of Nanometer SoCs. [Citation Graph (, )][DBLP]


  68. On Minimization of Test Application Time for RAS. [Citation Graph (, )][DBLP]


  69. Modified T-Flip-Flop based scan cell for RAS. [Citation Graph (, )][DBLP]


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