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Shinji Kimura: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Nobuhiro Doi, Takashi Horiyama, Masaki Nakanishi, Shinji Kimura
    Minimization of fractional wordlength on fixed-point conversion for high-level synthesis. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:80-85 [Conf]
  2. Shinji Kimura, Hiroyuki Kida, Kazuyoshi Takagi, Tatsumori Abematsu, Katsumasa Watanabe
    An application specific Java processor with reconfigurabilities. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:25-26 [Conf]
  3. Kazuhiro Nakamura, Shinji Maruoka, Shinji Kimura, Katsumasa Watanabe
    Multi-clock path analysis using propositional satisfiability. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:81-86 [Conf]
  4. Kazuhiro Nakamura, Qiang Zhu, Shinji Maruoka, Takashi Horiyama, Shinji Kimura, Katsumasa Watanabe
    A real-time 64-monosyllable recognition LSI with learning mechanism. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:31-32 [Conf]
  5. Kazuhiro Nakamura, Qiang Zhu, Shinji Maruoka, Takashi Horiyama, Shinji Kimura, Katsumasa Watanabe
    Speech recognition chip for monosyllables. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:396-399 [Conf]
  6. Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki
    FCSCAN: an efficient multiscan-based test compression technique for test cost reduction. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:653-658 [Conf]
  7. Xingwen Xu, Shinji Kimura, Kazunari Horikawa, Takehiko Tsuchiya
    Transition-based coverage estimation for symbolic model checking. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:1-6 [Conf]
  8. Youhua Shi, Shinji Kimura, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
    Alternative Run-Length Coding through Scan Chain Reconfiguration for Joint Minimization of Test Data Volume and Power Consumption in Scan Test. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:432-437 [Conf]
  9. Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, Shinji Kimura
    Low Power Test Compression Technique for Designs with Multiple Scan Chain. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:386-389 [Conf]
  10. Shinji Kimura, Yasufumi Itou, Makoto Hirao, Katsumasa Watanabe, Mitsuteru Yukishita, Akira Nagoya
    A Hardware/Software Codesign Method for a General Purpose Reconfigurable Co-Processor. [Citation Graph (0, 0)][DBLP]
    CODES, 1997, pp:147-152 [Conf]
  11. Shinji Kimura
    Residue BDD and Its Application to the Verification of Arithmetic Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:542-545 [Conf]
  12. Shinji Kimura, Takashi Horiyama, Masaki Nakanishi, Hirotsugu Kajihara
    Folding of logic functions and its application to look up table compaction. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:694-697 [Conf]
  13. Shinji Kimura, Shigemi Kashima, Hiromasa Haneda
    Precise timing verification of logic circuits under combined delay model. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:526-529 [Conf]
  14. Kazuhiro Nakamura, Kazuyoshi Takagi, Shinji Kimura, Katsumasa Watanabe
    Waiting false path analysis of sequential logic circuits for performance optimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:392-395 [Conf]
  15. Makoto Okada, Tatsuo Hiramatsu, Hiroshi Nakajima, Makoto Ozone, Katsunori Hirase, Shinji Kimura
    A Reconfigurable Processor Based on ALU Array Architecture with Limitation on the Interconnection. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  16. Xingwen Xu, Shinji Kimura, Kazunari Horikawa, Takehiko Tsuchiya
    Extended abstract: transition traversal coverage estimation for symbolic model checking. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2005, pp:259-260 [Conf]

  17. An objective and subjective evaluation of an autostereoscopic 3d display. [Citation Graph (, )][DBLP]


  18. Synthesis of parallel prefix adders considering switching activities. [Citation Graph (, )][DBLP]


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