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Seiji Kajihara: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yasumi Doi, Seiji Kajihara, Xiaoqing Wen, Lei Li, Krishnendu Chakrabarty
    Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:59-64 [Conf]
  2. Masayasu Fukunaga, Seiji Kajihara, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato
    A dynamic test compaction procedure for high-quality path delay testing. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:348-353 [Conf]
  3. Yasuo Sato, Shuji Hamada, Toshiyuki Maeda, Atsuo Takatori, Seiji Kajihara
    Evaluation of the statistical delay quality model. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:305-310 [Conf]
  4. Masayasu Fukunaga, Seiji Kajihara, Sadami Takeoka
    On Estimation of Fault Efficiency for Path Delay Faults. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:64-67 [Conf]
  5. Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita
    Test sequence compaction by reduced scan shift and retiming. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1995, pp:169-175 [Conf]
  6. Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita
    Partially Parallel Scan Chain for Test Length Reduction by Using Retiming Technique. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1996, pp:94-99 [Conf]
  7. Yoshinobu Higami, Seiji Kajihara, Shin-ya Kobayashi, Yuzo Takamatsu
    Techniques for Finding Xs in Test Sequences for Sequential Circuits and Applications to Test Length/Power Reduction. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:46-49 [Conf]
  8. Hideyuki Ichihara, Seiji Kajihara, Kozo Kinoshita
    An Efficient Procedure for Obtaining Implication Relations and Its Application to Redundancy Identification. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:58-63 [Conf]
  9. Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara
    On an Effective Selection of IDDQ Measurement Vectors for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1999, pp:147-152 [Conf]
  10. Kenichi Ichino, Takeshi Asakawa, Satoshi Fukumoto, Kazuhiko Iwasaki, Seiji Kajihara
    Hybrid BIST Using Partially Rotational Scan. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:379-384 [Conf]
  11. Seiji Kajihara, Atsushi Murakami, Tomohisa Kaneko
    On Compact Test Sets for Multiple Stuck-at Faults for Large Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1999, pp:20-24 [Conf]
  12. Seiji Kajihara, Tsutomu Sasao
    On the Adders with Minimum Tests. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1997, pp:10-15 [Conf]
  13. Seiji Kajihara, Takashi Shimono, Irith Pomeranz, Sudhakar M. Reddy
    Enhanced untestable path analysis using edge graphs. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:139-144 [Conf]
  14. Seiji Kajihara, Kenjiro Taniguchi, Kohei Miyase, Irith Pomeranz, Sudhakar M. Reddy
    Test Data Compression Using Don?t-Care Identification and Statistical Encoding. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:67-0 [Conf]
  15. Kohei Miyase, Seiji Kajihara
    Optimal Scan Tree Construction with Test Vector Modification for Test Compression. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:136-141 [Conf]
  16. Kohei Miyase, Seiji Kajihara, Sudhakar M. Reddy
    Multiple Scan Tree Design with Test Vector Modification. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:76-81 [Conf]
  17. Kohei Miyase, Kenta Terashima, Seiji Kajihara, Xiaoqing Wen, Sudhakar M. Reddy
    On Improving Defect Coverage of Stuck-at Fault Tests. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:216-223 [Conf]
  18. Yun Shao, Sudhakar M. Reddy, Seiji Kajihara, Irith Pomeranz
    An Efficient Method to Identify Untestable Path Delay Faults. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:233-238 [Conf]
  19. Seiji Kajihara, Masayasu Fukunaga, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato
    Path delay test compaction with process variation tolerance. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:845-850 [Conf]
  20. Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy
    Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:102-106 [Conf]
  21. Seiji Kajihara, Kenjiro Taniguchi, Irith Pomeranz, Sudhakar M. Reddy
    Test Data Compression Using Don't-Care Identification and Statistical Encoding. [Citation Graph (0, 0)][DBLP]
    DELTA, 2002, pp:413-416 [Conf]
  22. Kohei Miyase, Seiji Kajihara, Sudhakar M. Reddy
    A Method of Static Test Compaction Based on Don't Care Identification. [Citation Graph (0, 0)][DBLP]
    DELTA, 2002, pp:392-395 [Conf]
  23. Seiji Kajihara, Haruko Shiba, Kozo Kinoshita
    Removal of Redundancy in Logic Circuits under Classification of Undetectable Faults. [Citation Graph (0, 0)][DBLP]
    FTCS, 1992, pp:263-270 [Conf]
  24. Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita
    Synthesis for Testability by Sequential Redundancy Removal Using Retiming. [Citation Graph (0, 0)][DBLP]
    FTCS, 1995, pp:33-40 [Conf]
  25. Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara
    On Test Generation with A Limited Number of Tests. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:12-15 [Conf]
  26. Seiji Kajihara, Kohei Miyase
    On Identifying Don't Care Inputs of Test Patterns for Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:364-369 [Conf]
  27. Seiji Kajihara, Tetsuji Sumioka, Kozo Kinoshita
    Test generation for multiple faults based on parallel vector pair analysis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:436-439 [Conf]
  28. Xiaoqing Wen, Tokiharu Miyoshi, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita
    On per-test fault diagnosis using the X-fault model. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:633-640 [Conf]
  29. Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu, Seiji Kajihara, Irith Pomeranz
    A Method to Find Don't Care Values in Test Sequences for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:397-0 [Conf]
  30. Seiji Kajihara, Yasumi Doi, Lei Li, Krishnendu Chakrabarty
    On Combining Pinpoint Test Set Relaxation and Run-Length Codes for Reducing Test Data Volume. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:387-396 [Conf]
  31. Kohei Miyase, Seiji Kajihara, Irith Pomeranz, Sudhakar M. Reddy
    Don't-Care Identification on Specific Bits of Test Patterns. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:194-199 [Conf]
  32. Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita
    Reduced Scan Shift: A New Testing Method for Sequential Circuit. [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:624-630 [Conf]
  33. Atsushi Murakami, Seiji Kajihara, Tsutomu Sasao, Irith Pomeranz, Sudhakar M. Reddy
    Selection of potentially testable path delay faults for test generation. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:376-384 [Conf]
  34. Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara, Atsushi Murakami, Sadami Takeoka, Mitsuyasu Ohta
    On validating data hold times for flip-flops in sequential circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:317-325 [Conf]
  35. Sudhakar M. Reddy, Irith Pomeranz, Huaxing Tang, Seiji Kajihara, Kozo Kinoshita
    On Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:83-89 [Conf]
  36. Dong Hyun Baik, Kewal K. Saluja, Seiji Kajihara
    Random Access Scan: A solution to test power, test data volume and test time. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:883-888 [Conf]
  37. Seiji Kajihara, Kozo Kinoshita, Irith Pomeranz, Sudhakar M. Reddy
    A Method for Identifying Robust Dependent and Functionally Unsensitizable Paths. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:82-87 [Conf]
  38. Seiji Kajihara, Kewal K. Saluja
    On Test Pattern Compaction Using Random Pattern Fault Simulation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:464-469 [Conf]
  39. Lei Li, Krishnendu Chakrabarty, Seiji Kajihara, Shivakumar Swaminathan
    Efficient Space/Time Compression to Reduce Test Data Volume and Testing Time for IP Cores. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:53-58 [Conf]
  40. Seiji Kajihara, Koji Ishida, Kohei Miyase
    Test Vector Modification for Power Reduction during Scan Testing. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:160-165 [Conf]
  41. Sudhakar M. Reddy, Kohei Miyase, Seiji Kajihara, Irith Pomeranz
    On Test Data Volume Reduction for Multiple Scan Chain Designs. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:103-110 [Conf]
  42. Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara
    On the effects of test compaction on defect coverage. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:430-437 [Conf]
  43. Remata S. Reddy, Irith Pomeranz, Sudhakar M. Reddy, Seiji Kajihara
    Compact test generation for bridging faults under I/sub DDQ/ testing. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:310-316 [Conf]
  44. Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Khader S. Abdel-Hafez, Kozo Kinoshita
    A New ATPG Method for Efficient Capture Power Reduction During Scan Testing. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:58-65 [Conf]
  45. Xiaoqing Wen, Yoshiyuki Yamashita, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita
    On Low-Capture-Power Test Generation for Scan Testing. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:265-270 [Conf]
  46. Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita
    Resynthesis for sequential circuits designed with a specified initial state. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:152-157 [Conf]
  47. Takeshi Asakawa, Kazuhiko Iwasaki, Seiji Kajihara
    BIST-oriented test pattern generator for detection of transition faults. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 2003, v:34, n:3, pp:76-84 [Journal]
  48. Yoshinobu Higami, Seiji Kajihara, Hideyuki Ichihara, Yuzo Takamatsu
    Test cost reduction for logic circuits: Reduction of test data volume and test application time. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 2005, v:36, n:6, pp:69-83 [Journal]
  49. Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara
    On invariant implication relations for removing partial circuits. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 1997, v:28, n:7, pp:39-47 [Journal]
  50. Atsushi Yoshikawa, Seiji Kajihara, Masahiro Numa, Kozo Kinoshita
    A diagnosis method for single logic design errors in gate-level combinational circuits. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 1997, v:28, n:6, pp:30-39 [Journal]
  51. Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy
    Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:12, pp:1496-1504 [Journal]
  52. Kohei Miyase, Seiji Kajihara
    XID: Don't care identification of test patterns for combinational circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:2, pp:321-326 [Journal]
  53. Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara
    Compact test sets for high defect coverage. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:8, pp:923-930 [Journal]
  54. Sudhakar M. Reddy, Kohei Miyase, Seiji Kajihara, Irith Pomeranz
    On test data volume reduction for multiple scan chain designs. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2003, v:8, n:4, pp:460-469 [Journal]
  55. Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Seiji Kajihara, Yuji Ohsumi, Kewal K. Saluja
    Critical-Path-Aware X-Filling for Effective IR-Drop Reduction in At-Speed Scan Testing. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:527-532 [Conf]
  56. Xiaoqing Wen, Tatsuya Suzuki, Seiji Kajihara, Kohei Miyase, Yoshihiro Minamoto, Laung-Terng Wang, Kewal K. Saluja
    Efficient Test Set Modification for Capture Power Reduction. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2005, v:1, n:3, pp:319-330 [Journal]

  57. CAT: A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing. [Citation Graph (, )][DBLP]


  58. Diagnosis of Realistic Defects Based on the X-Fault Model. [Citation Graph (, )][DBLP]


  59. Estimation of delay test quality and its application to test generation. [Citation Graph (, )][DBLP]


  60. Effective IR-drop reduction in at-speed scan testing using Distribution-Controlling X-Identification. [Citation Graph (, )][DBLP]


  61. A novel post-ATPG IR-drop reduction scheme for at-speed scan testing in broadcast-scan-based test compression environment. [Citation Graph (, )][DBLP]


  62. Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation. [Citation Graph (, )][DBLP]


  63. A GA-Based Method for High-Quality X-Filling to Reduce Launch Switching Activity in At-speed Scan Testing. [Citation Graph (, )][DBLP]


  64. On estimation of NBTI-Induced delay degradation. [Citation Graph (, )][DBLP]


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