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Sudhakar Muddu: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Feodor F. Dragan, Andrew B. Kahng, Ion I. Mandoiu, Sudhakar Muddu, Alexander Zelikovsky
    Provably good global buffering by multi-terminal multicommodity flow approximation. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:120-125 [Conf]
  2. Andrew B. Kahng, Sudhakar Muddu
    Delay Analysis of VLSI Interconnections Using the Diffusion Equation Model. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:563-569 [Conf]
  3. Andrew B. Kahng, Sudhakar Muddu
    Analysis of RC Interconnections Under Ramp Input. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:533-538 [Conf]
  4. Andrew B. Kahng, Sudhakar Muddu, Egino Sarto
    On switch factor based analysis of coupled RC interconnects. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:79-84 [Conf]
  5. Andrew B. Kahng, Sudhakar Muddu, Egino Sarto, Rahul Sharma
    Interconnect Tuning Strategies for High-Performance Ics. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:471-478 [Conf]
  6. Yu Cao, Chenming Hu, Xuejue Huang, Andrew B. Kahng, Sudhakar Muddu, Dirk Stroobandt, Dennis Sylvester
    Effects of Global Interconnect Optimizations on Performance Estimation of Deep Submicron Design. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:56-61 [Conf]
  7. Feodor F. Dragan, Andrew B. Kahng, Ion I. Mandoiu, Sudhakar Muddu, Alexander Zelikovsky
    Provably Good Global Buffering Using an Available Buffer Block Plan. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:104-109 [Conf]
  8. Andrew B. Kahng, Kei Masuko, Sudhakar Muddu
    Analytical delay models for VLSI interconnects under ramp input. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:30-36 [Conf]
  9. Andrew B. Kahng, Sudhakar Muddu
    New efficient algorithms for computing effective capacitance. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:147-151 [Conf]
  10. Andrew B. Kahng, Sudhakar Muddu, Niranjan Pol, Devendra Vidhani
    Noise Model for Multiple Segmented Coupled RC Interconnects. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:145-150 [Conf]
  11. Sudhakar Muddu
    Estimation needs for future networking systems interconnect. [Citation Graph (0, 0)][DBLP]
    SLIP, 2002, pp:41-44 [Conf]
  12. Andrew B. Kahng, Sudhakar Muddu
    Improved Effective Capacitance Computations for Use in Logic and Layout Optimization. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:578-583 [Conf]
  13. Andrew B. Kahng, Sudhakar Muddu, Egino Sarto
    Interconnect Optimization Strategies for High-Performance VLSI Designs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:464-469 [Conf]
  14. Feodor F. Dragan, Andrew B. Kahng, Ion I. Mandoiu, Sudhakar Muddu, Alexander Zelikovsky
    Practical Approximation Algorithms for Separable Packing Linear Programs. [Citation Graph (0, 0)][DBLP]
    WADS, 2001, pp:325-337 [Conf]
  15. Feodor F. Dragan, Andrew B. Kahng, Ion I. Mandoiu, Sudhakar Muddu, Alexander Zelikovsky
    Provably good global buffering by generalized multiterminalmulticommodity flow approximation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:3, pp:263-274 [Journal]
  16. Andrew B. Kahng, Sudhakar Muddu
    An analytical delay model for RLC interconnects. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:12, pp:1507-1514 [Journal]
  17. Andrew B. Kahng, Sudhakar Muddu
    Analysis of RC interconnections under ramp input. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1997, v:2, n:2, pp:168-192 [Journal]

  18. Optimal equivalent circuits for interconnect delay calculations using moments. [Citation Graph (, )][DBLP]


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