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Kartikeya Mayaram: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Xiaochun Duan, Kartikeya Mayaram
    A new approach for ring oscillator simulation using the harmonic balance method. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:236-239 [Conf]
  2. Zhao Li, Ravikanth Suravarapu, Roy Hartono, Sambuddha Bhattacharya, Kartikeya Mayaram, C.-J. Richard Shi
    CrtSmile: a CAD tool for CMOS RF transistor substrate modeling incorporating layout effects. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:163-168 [Conf]
  3. Douglas Braun, Jeffrey L. Burns, Srinivas Devadas, Hi-Keung Tony Ma, Kartikeya Mayaram, Fabio Romeo, Alberto L. Sangiovanni-Vincentelli
    Chameleon: a new multi-layer channel router. [Citation Graph (0, 0)][DBLP]
    DAC, 1986, pp:495-502 [Conf]
  4. Chenggang Xu, Ranjit Gharpurey, Terri S. Fiez, Kartikeya Mayaram
    A green function-based parasitic extraction method for inhomogeneous substrate layers. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:141-146 [Conf]
  5. Alicia Manthe, Zhao Li, C.-J. Richard Shi, Kartikeya Mayaram
    Symbolic Analysis of Nonlinear Analog Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11108-11109 [Conf]
  6. Xiaochun Duan, Kartikeya Mayaram
    Frequency domain simulation of high-Q oscillators with homotopy methods. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:683-686 [Conf]
  7. Kartikeya Mayaram, Ping Yang, Jue-Hsien Chern
    Transient Three-Dimensional Mixed-Level Circuit and Device Simulation: Algorithms and Applications. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:112-115 [Conf]
  8. Kartikeya Mayaram, Ping Yang, Jue-Hsien Chern, Richard Burch, Lawrence A. Arledge Jr., Paul F. Cox
    A Parallel Block-Diagonal Preconditioned Conjugate-Gradient Solution Algorithm for Circuit and Device Simulations. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:446-449 [Conf]
  9. Anil Samavedam, Kartikeya Mayaram, Terri S. Fiez
    A scalable substrate noise coupling model for mixed-signal ICs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:128-131 [Conf]
  10. Manas Behera, Volodymyr Kratyuk, Yutao Hu, Kartikeya Mayaram
    Accurate simulation of phase noise in RF MEMS VCOs. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2004, pp:677-680 [Conf]
  11. Volodymyr Kratyuk, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram
    A low spur fractional-N frequency synthesizer architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2807-2810 [Conf]
  12. Volodymyr Kratyuk, Igor Vytyaz, Un-Ku Moon, Kartikeya Mayaram
    Analysis of supply and ground noise sensitivity in ring and LC oscillators. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5986-5989 [Conf]
  13. Ajit Sharma, Chenggang Xu, Wen Kung Chu, Nishath K. Verghese, Terri S. Fiez, Kartikeya Mayaram
    A predictive methodology for accurate substrate parasitic extraction. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:149-152 [Conf]
  14. Robert Shreeve, Terri S. Fiez, Kartikeya Mayaram
    A physical and analytical model for substrate noise coupling analysis. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:157-160 [Conf]
  15. Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram
    An improved Z-parameter macro model for substrate noise coupling. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:161-164 [Conf]
  16. Anil Samavedam, Kartikeya Mayaram, Terri S. Fiez
    Design-oriented substrate noise coupling macromodels for heavily doped CMOS processes. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 1999, pp:218-221 [Conf]
  17. Husni M. Habal, Terri S. Fiez, Kartikeya Mayaram
    An accurate and efficient estimation of switching noise in synchronous digital circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:485-488 [Conf]
  18. Wanliang Ma, L. Trajkovic, Kartikeya Mayaram
    HomSSPICE: a homotopy-based circuit simulator for periodic steady-state analysis of oscillators. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2002, pp:645-648 [Conf]
  19. V. Chandrasekhar, Kartikeya Mayaram
    Analysis of CMOS RF LNAs with ESD protection. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:799-802 [Conf]
  20. N. Barton, D. Ozis, Terri S. Fiez, Kartikeya Mayaram
    Analysis of jitter in ring oscillators due to deterministic noise. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:393-396 [Conf]
  21. N. Seshan, J. Rajagopalan, Kartikeya Mayaram
    Design of low power 2.4 GHz CMOS LC oscillators with low phase-noise and large tuning range. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:409-412 [Conf]
  22. D. Ozis, Kartikeya Mayaram, Terri S. Fiez
    An efficient modeling approach for substrate noise coupling analysis. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:237-240 [Conf]
  23. Yutao Hu, Kartikeya Mayaram
    An efficient algorithm for large-signal frequency-domain coupled device and circuit simulation [RF circuits]. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:329-332 [Conf]
  24. Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram
    Coupled Simulation of Circuit and Piezoelectric Laminates. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:369-372 [Conf]
  25. Kartikeya Mayaram
    CEDA Currents. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2006, v:23, n:2, pp:168-171 [Journal]
  26. Yutao Hu, Kartikeya Mayaram
    Comparison of Algorithms for Frequency Domain Coupled Device and Circuit Simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2571-2578 [Journal]
  27. Douglas Braun, Jeffrey L. Burns, Fabio Romeo, Alberto L. Sangiovanni-Vincentelli, Kartikeya Mayaram, Srinivas Devadas, Hi-Keung Tony Ma
    Techniques for multilayer channel routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:6, pp:698-712 [Journal]
  28. Richard Burch, Ping Yang, Paul F. Cox, Kartikeya Mayaram
    A new matrix solution technique for general circuit simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:2, pp:225-241 [Journal]
  29. Xiaochun Duan, Kartikeya Mayaram
    An efficient and robust method for ring-oscillator simulation using the harmonic-balance method. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:8, pp:1225-1233 [Journal]
  30. Kartikeya Mayaram, Jue-Hsien Chern, Ping Yang
    Algorithms for transient three-dimensional mixed-level circuit and device simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:11, pp:1726-1733 [Journal]
  31. Kartikeya Mayaram, Donald O. Pederson
    Coupling algorithms for mixed-level circuit and device simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:8, pp:1003-1012 [Journal]
  32. Suet Fong Tin, Ashraf A. Osman, Kartikeya Mayaram
    Comments on "A small-signal MOSFET model for radio frequency IC applications". [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:4, pp:372-374 [Journal]
  33. Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram
    On the numerical stability of Green's function for substrate coupling in integrated circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:4, pp:653-658 [Journal]
  34. Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram
    An error control method for application of the discrete cosine transform to extraction of substrate parasitics in ICs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:5, pp:932-938 [Journal]
  35. Husni M. Habal, Kartikeya Mayaram, Terri S. Fiez
    Accurate and efficient simulation of synchronous digital switching noise in systems on a chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:3, pp:330-338 [Journal]
  36. Ajit Sharma, P. Birrer, S. K. Arunachalam, Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram
    Accurate Prediction of Substrate Parasitics in Heavily Doped CMOS Processes Using a Calibrated Boundary Element Solver. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:7, pp:843-851 [Journal]
  37. Igor Vytyaz, David C. Lee, Suihua Lu, Amit Mehrotra, Un-Ku Moon, Kartikeya Mayaram
    Parameter Finding Methods for Oscillators with a Specified Oscillation Frequency. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:424-429 [Conf]
  38. Igor Vytyaz, David C. Lee, Suihua Lu, Amit Mehrotra, Un-Ku Moon, Kartikeya Mayaram
    Periodic Steady-State Analysis of Oscillators with a Specified Oscillation Frequency. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1073-1076 [Conf]
  39. James Ayers, Kartikeya Mayaram, Terri S. Fiez
    A Low Power BFSK Super-Regenerative Transceiver. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3099-3102 [Conf]
  40. Raghuram Jonnalagedda, Kartikeya Mayaram
    Design of Very Low Noise 4.2GHz Clapp VCOs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2862-2865 [Conf]
  41. James Ayers, Kartikeya Mayaram, Terri S. Fiez
    Tradeoffs in the Design of CMOS Receivers for Low Power Wireless Sensor Networks. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1345-1348 [Conf]
  42. Maneesha Yellepeddi, Kartikeya Mayaram
    Issues in the Design and Simulation of a MEMS VCO based Phase-Locked Loop. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1553-1556 [Conf]
  43. Janakiram G. Sankaranarayanan, Kartikeya Mayaram
    Noise Simulation and Modeling for MEMS Varactor Based RF VCOs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2698-2701 [Conf]
  44. Ting Wu, Un-Ku Moon, Kartikeya Mayaram
    Dependence of LC VCO oscillation frequency on bias current. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]

  45. Periodic Steady-State Analysis Augmented with Design Equality Constraints. [Citation Graph (, )][DBLP]


  46. Sensitivity analysis for oscillators. [Citation Graph (, )][DBLP]


  47. An FMDLL based dual-loop frequency synthesizer for 5 GHz WLAN applications. [Citation Graph (, )][DBLP]


  48. Parameter variation analysis for voltage controlled oscillators in phase-locked loops. [Citation Graph (, )][DBLP]


  49. Comparison of supply noise and substrate noise reduction in SiGe BiCMOS and FDSOI processes. [Citation Graph (, )][DBLP]


  50. Neural Network Design for Behavioral Model Generation with Shape Preserving Properties. [Citation Graph (, )][DBLP]


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