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David Duarte: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. David Duarte, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mary Jane Irwin
    Evaluating Run-Time Techniques for Leakage Power Reduction. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:31-38 [Conf]
  2. Yuh-Fang Tsai, David Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin
    Implications of technology scaling on leakage reduction techniques. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:187-190 [Conf]
  3. David Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin
    A Complete Phase-Locked Loop Power Consumption Model. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1108- [Conf]
  4. David Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin, Hyun Suk Kim, G. McFarland
    Impact of Scaling on the Effectiveness of Dynamic Power Reduction Schemes. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:382-387 [Conf]
  5. David Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin
    Impact of Technology Scaling in the Clock System Power. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2002, pp:59-64 [Conf]
  6. Wei Zhang 0002, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, David Duarte, Yuh-Fang Tsai
    Exploiting VLIW schedule slacks for dynamic and leakage energy reduction. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:102-113 [Conf]
  7. David Duarte, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mary Jane Irwin
    Evaluating Run-Time Techniques for Leakage Power Reduction. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:31-38 [Conf]
  8. David Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut T. Kandemir
    Formulation and Validation of an Energy Dissipation Model for the Clock Generation Circuitry and Distribution Networks. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:248-253 [Conf]
  9. Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Hyun Suk Kim, Wu Ye, David Duarte
    Evaluating Integrated Hardware-Software Optimizations Using a Unified Energy Estimation Framework. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:1, pp:59-76 [Journal]
  10. Wei Zhang 0002, Yuh-Fang Tsai, David Duarte, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
    Reducing dynamic and leakage energy in VLIW architectures. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2006, v:5, n:1, pp:1-28 [Journal]

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