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Takayasu Sakurai: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Nguyen Minh Duc, Takayasu Sakurai
    Compact yet high performance (CyHP) library for short time-to-market with new technologies. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:475-480 [Conf]
  2. Koichi Ishida, Atit Tamtrakarn, Takayasu Sakurai
    A 0.5-V sigma-delta modulator using analog T-switch scheme for the subthreshold leakage suppression. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:98-99 [Conf]
  3. Hiroshi Kawaguchi, Takayasu Sakurai
    Delay and Noise Formulas for Capacitively Coupled Distributed RC Lines. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:35-43 [Conf]
  4. Seongsoo Lee, Takayasu Sakurai
    Run-time power control scheme using software feedback loop for low-power real-time application. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:381-386 [Conf]
  5. Koichi Nose, Takayasu Sakurai
    Optimization of VDD and VTH for low-power and high speed applications. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:469-474 [Conf]
  6. Takayasu Sakurai
    Design challenges for 0.1um and beyond: embedded tutorial. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:553-558 [Conf]
  7. Koichi Nose, Takayasu Sakurai
    Integrated Current Sensing Device for Micro IDDQ Test. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:323-326 [Conf]
  8. Seongsoo Lee, Takayasu Sakurai
    Run-time voltage hopping for low-power real-time systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:806-809 [Conf]
  9. Jan M. Rabaey, Dennis Sylvester, David Blaauw, Kerry Bernstein, Jerry Frenkil, Mark Horowitz, Wolfgang Nebel, Takayasu Sakurai, Andrew Yang
    Reshaping EDA for power. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:15- [Conf]
  10. Youngsoo Shin, Takayasu Sakurai
    Coupling-Driven Bus Design for Low-Power Application-Specific Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:750-753 [Conf]
  11. Takayasu Sakurai
    Minimizing power across multiple technology and design levels. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:24-27 [Conf]
  12. Youngsoo Shin, Kiyoung Choi, Takayasu Sakurai
    Power Optimization of Real-Time Embedded Systems on Variable Speed Processors. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:365-368 [Conf]
  13. Takayasu Sakurai
    High-Speed Circuit Design with Scaled-Down MOSFET's and Low Supply Voltage. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1487-1490 [Conf]
  14. Canh Quang Tran, Hiroshi Kawaguchi, Takayasu Sakurai
    More than two orders of magnitude leakage current reduction in look-up table for FPGAs. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4701-4704 [Conf]
  15. Hiroshi Kawaguchi, Gang Zhang, Seongsoo Lee, Takayasu Sakurai
    An LSI for VDD-hopping and MPEG4 system based on the chip. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:918-921 [Conf]
  16. Kyeong-Sik Min, Young-Hee Kim, Jin-Hong Ahn, Jin-Yong Chung, T. Sakurai
    CMOS charge pumps using cross-coupled charge transfer switches with improved voltage pumping gain and low gate-oxide stress for low-voltage memory circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:545-548 [Conf]
  17. Masayuki Hirabayashi, Koichi Nose, Takayasu Sakurai
    Design methodology and optimization strategy for dual-VTH scheme using commercially available tools. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:283-286 [Conf]
  18. Takashi Inukai, Toshiro Hiramoto, Takayasu Sakurai
    Variable threshold CMOS (VTCMOS) in series connected circuits. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:201-206 [Conf]
  19. Tadahiro Kuroda, Tetsuya Fujita, Shinji Mita, Toshiaki Mori, Kenji Matsuo, Masakazu Kakumu, Takayasu Sakurai
    Substrate noise influence on circuit performance in variable threshold-voltage scheme. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:309-312 [Conf]
  20. Koichi Nose, Soo-Ik Chae, Takayasu Sakurai
    Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage (poster session). [Citation Graph (0, 0)][DBLP]
    ISLPED, 2000, pp:228-230 [Conf]
  21. Koichi Nose, Takayasu Sakurai
    Power-conscious interconnect buffer optimization with improved modeling of driver MOSFET and Its implications to bulk and SOI CMOS technology. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:24-29 [Conf]
  22. Youngsoo Shin, Takayasu Sakurai
    Estimation of power distribution in VLSI interconnects. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:370-375 [Conf]
  23. Takayasu Sakurai
    Reducing Power Consumption of CMOS VLSI's through VDD and VTH Control. [Citation Graph (0, 0)][DBLP]
    ISQED, 2000, pp:417-424 [Conf]
  24. Takayasu Sakurai
    Low-Power and High-Speed V VLSI Design with Low Supply Voltage through Cooperation between Levels (invited). [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:445-450 [Conf]
  25. Seongsoo Lee, Seungjun Lee, Takayasu Sakurai
    Energy-Constrained VDD Hopping Scheme with Run-Time Power Estimation for Low-Power Real-Time VLSI Systems. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2002, v:11, n:6, pp:601-620 [Journal]
  26. Keisuke Toyama, Satoshi Misaka, Kazuo Aisaka, Toshiyuki Aritsuka, Kunio Uchiyama, Koichiro Ishibashi, Hiroshi Kawaguchi, Takayasu Sakurai
    Frequency-voltage cooperative CPU power control: A design rule and its application by feedback prediction. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 2005, v:36, n:6, pp:39-48 [Journal]
  27. Koichi Nose, Takayasu Sakurai
    Analysis and future trend of short-circuit power. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:9, pp:1023-1030 [Journal]
  28. Takayasu Sakurai, Bill Lin, A. Richard Newton
    Fast simulated diffusion: an optimization algorithm for multiminimum problems and its application to MOSFET model parameter extraction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:2, pp:228-234 [Journal]
  29. Hiroshi Kawaguchi, Youngsoo Shin, Takayasu Sakurai
    /spl mu/ITRON-LP: power-conscious real-time OS based on cooperative voltage scaling for multimedia applications. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Multimedia, 2005, v:7, n:1, pp:67-74 [Journal]
  30. Kyeong-Sik Min, Hun-Dae Choi, H.-Y. Choi, Hiroshi Kawaguchi, Takayasu Sakurai
    Leakage-suppressed clock-gating circuit with Zigzag Super Cut-off CMOS (ZSCCMOS) for leakage-dominant sub-70-nm and sub-1-V-V/sub DD/ LSIs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:4, pp:430-435 [Journal]

  31. A 100Mbps, 0.19mW asynchronous threshold detector with DC power-free pulse discrimination for impulse UWB receiver. [Citation Graph (, )][DBLP]


  32. Meeting with the Forthcoming IC Design "The Era of Power, Variability and NRE Explosion and a Bit of the Future". [Citation Graph (, )][DBLP]


  33. Increasing minimum operating voltage (VDDmin) with number of CMOS logic gates and experimental verification with up to 1Mega-stage ring oscillators. [Citation Graph (, )][DBLP]


  34. Next-generation power-aware design. [Citation Graph (, )][DBLP]


  35. Inductor design of 20-V boost converter for low power 3D solid state drive with NAND flash memories. [Citation Graph (, )][DBLP]


  36. Dependence of Minimum Operating Voltage (VDDmin) on Block Size of 90-nm CMOS Ring Oscillators and its Implications in Low Power DFM. [Citation Graph (, )][DBLP]


  37. Meeting with the forthcoming IC design. [Citation Graph (, )][DBLP]


  38. A capacitive coupling interface with high sensitivity for wireless wafer testing. [Citation Graph (, )][DBLP]


  39. Effect of resistance of TSV's on performance of boost converter for low power 3D SSD with NAND flash memories. [Citation Graph (, )][DBLP]


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