The SCEAS System
Navigation Menu

Search the dblp DataBase


Hiroyuki Tomiyama: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Nikil D. Dutt, Alexandru Nicolau, Hiroyuki Tomiyama, Ashok Halambi
    New directions in compiler technology for embedded systems (embedded tutorial). [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:409-414 [Conf]
  2. Prabhat Mishra, Ashok Halambi, Peter Grun, Nikil D. Dutt, Alexandru Nicolau, Hiroyuki Tomiyama
    Automatic Modeling and Validation of Pipeline Specifications driven by an Architecture Description Language. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:458-466 [Conf]
  3. Hiroyuki Tomiyama, Hiroto Yasuura
    Module Selection Using Manufacturing Information. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:275-281 [Conf]
  4. Shinya Honda, Takayuki Wakabayashi, Hiroyuki Tomiyama, Hiroaki Takada
    RTOS-centric hardware/software cosimulator for embedded system design. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:158-163 [Conf]
  5. Hiroyuki Tomiyama, Nikil D. Dutt
    Program path analysis to bound cache-related preemption delay in preemptive real-time systems. [Citation Graph (0, 0)][DBLP]
    CODES, 2000, pp:67-71 [Conf]
  6. Barry Shackleford, Mitsuhiro Yasuda, Etsuko Okushi, Hisao Koizumi, Hiroyuki Tomiyama, Hiroto Yasuura
    Memory-CPU Size Optimization for Embedded System Designs. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:246-251 [Conf]
  7. Prabhat Mishra, Nikil D. Dutt, Alexandru Nicolau, Hiroyuki Tomiyama
    Automatic Verification of In-Order Execution In Microprocessors with Fragmented Pipelines and Multicycle Functional Units. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:36-43 [Conf]
  8. Hiroyuki Tomiyama, Tohru Ishihara, Akihiko Inoue, Hiroto Yasuura
    Instruction Scheduling for Power Reduction in Processor-Based System Design. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:855-860 [Conf]
  9. Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada
    Function Call Optimization in Behavioral Synthesis. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:522-529 [Conf]
  10. Shan Ding, Naohiko Murakami, Hiroyuki Tomiyama, Hiroaki Takada
    A GA-based scheduling method for FlexRay systems. [Citation Graph (0, 0)][DBLP]
    EMSOFT, 2005, pp:110-113 [Conf]
  11. Hiroyuki Tomiyama, Hiroaki Takada, Nikil D. Dutt
    Data Organization Exploration for Low-Energy Address Buses. [Citation Graph (0, 0)][DBLP]
    ESTImedia, 2003, pp:128-133 [Conf]
  12. Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, Katsuya Ishii
    Complexity-constrainted partitioning of sequential programs for efficient behavioral synthesis. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:365-370 [Conf]
  13. Takanori Okuma, Hiroyuki Tomiyama, Akihiko Inoue, Eko Fajar, Hiroto Yasuura
    Instruction Encoding Techniques for Area Minimization of Instruction ROM. [Citation Graph (0, 0)][DBLP]
    ISSS, 1998, pp:125-130 [Conf]
  14. Hiroyuki Tomiyama, Akihiko Inoue, Hiroto Yasuura
    Statistical Performance-Driven Module Binding in High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    ISSS, 1998, pp:66-71 [Conf]
  15. Hiroyuki Tomiyama, Hiroto Yasuura
    Size-Constrained Code Placement for Cache Miss Rate Reduction. [Citation Graph (0, 0)][DBLP]
    ISSS, 1996, pp:96-104 [Conf]
  16. Hiroto Yasuura, Hiroyuki Tomiyama, Takanori Okuma, Yun Cao
    Data Memory Design Considering Effective Bitwidth for Low-Energy Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:201-206 [Conf]
  17. Hiroshi Miyamoto, Shinichi Iiyama, Hiroyuki Tomiyama, Hiroaki Takada, Hiroshi Nakashima
    An Efficient Search Algorithm of Worst-Case Cache Flush Timings. [Citation Graph (0, 0)][DBLP]
    RTCSA, 2005, pp:45-52 [Conf]
  18. Anupam Datta, Sidharth Choudhury, Anupam Basu, Hiroyuki Tomiyama, Nikil Dutt
    Satisfying Timing Constraints of Preemptive Real-Time Tasks through Task Layout Technique. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:97-102 [Conf]
  19. Prabhat Mishra, Hiroyuki Tomiyama, Ashok Halambi, Peter Grun, Nikil D. Dutt, Alexandru Nicolau
    Automatic Modeling and Validation of Pipeline Specifications Driven by an Architecture Description Language. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:458-0 [Conf]
  20. Hiroto Yasuura, Hiroyuki Tomiyama, Akihiko Inoue, Eko Fajar
    Embedded System Design Using Soft-Core Processor and Valen-C. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 1998, v:14, n:3, pp:587-603 [Journal]
  21. Hiroyuki Tomiyama, Hiroto Yasuura
    Code placement techniques for cache miss rate reduction. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1997, v:2, n:4, pp:410-429 [Journal]
  22. Takashi Furukawa, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada
    A Hardware/Software Cosimulator with RTOS Supports for Multiprocessor Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ICESS, 2007, pp:283-294 [Conf]
  23. Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, Katsuya Ishii
    Behavioral Synthesis of Double-Precision Floating-Point Adders with Function-Level Transformations: A Case Study. [Citation Graph (0, 0)][DBLP]
    ICESS, 2007, pp:261-270 [Conf]
  24. Shan Ding, Hiroyuki Tomiyama, Hiroaki Takada
    Scheduling Algorithms for I/O Blockings with a Multi-frame Task Model. [Citation Graph (0, 0)][DBLP]
    RTCSA, 2007, pp:386-393 [Conf]
  25. Gang Zeng, Hiroyuki Tomiyama, Hiroaki Takada
    Power Optimization for Embedded System Idle Time in the Presence of Periodic Interrupt Services. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:241-254 [Conf]

  26. Analyzing and optimizing energy efficiency of algorithms on DVS systems a first step towards algorithmic energy minimization. [Citation Graph (, )][DBLP]

  27. RTOS and Codesign Toolkit for Multiprocessor Systems-on-Chip. [Citation Graph (, )][DBLP]

  28. Partitioning and allocation of scratch-pad memory for priority-based preemptive multi-task systems. [Citation Graph (, )][DBLP]

  29. Improved Policies for Drowsy Caches in Embedded Processors. [Citation Graph (, )][DBLP]

  30. Aggressive Register Unsharing Based on SSA Transformation for Clock Enhancement in High-Level Synthesis. [Citation Graph (, )][DBLP]

  31. A Software Framework for Energy and Performance Tradeoff in Fixed-Priority Hard Real-Time Embedded Systems. [Citation Graph (, )][DBLP]

  32. A Generalized Framework for System-Wide Energy Savings in Hard Real-Time Embedded Systems. [Citation Graph (, )][DBLP]

  33. CHStone: A benchmark program suite for practical C-based high-level synthesis. [Citation Graph (, )][DBLP]

  34. Practical Energy-Aware Scheduling for Real-Time Multiprocessor Systems. [Citation Graph (, )][DBLP]

Search in 0.084secs, Finished in 0.087secs
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002