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Wolfgang Günther: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler
    Minimization of the expected path length in BDDs based on local changes. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:865-870 [Conf]
  2. Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler
    Combining ordered best-first search with branch and bound for exact BDD minimization. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:875-878 [Conf]
  3. Wolfgang Günther, Rolf Drechsler
    Minimization of Free BDDs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:323-326 [Conf]
  4. Wolfgang Günther, Andreas Hett, Bernd Becker
    Application of linearly transformed BDDs in sequential verification. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:91-96 [Conf]
  5. Ilia Polian, Wolfgang Günther, Bernd Becker
    Efficient Pattern-Based Verification of Connections to IP Cores . [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:443-448 [Conf]
  6. Rolf Drechsler, Nicole Drechsler, Wolfgang Günther
    Fast Exact Minimization of BDDs. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:200-205 [Conf]
  7. Rolf Drechsler, Wolfgang Günther
    Using Lower Bounds During Dynamic BDD Minimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:29-32 [Conf]
  8. Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler
    Combination of Lower Bounds in Exact BDD Minimization. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10758-10763 [Conf]
  9. Rolf Drechsler, Wolfgang Günther, Lothar Linhard, Gerhard Angst
    Level Assignment for Displaying Combinational Logic. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:148-151 [Conf]
  10. Rolf Drechsler, Wolfgang Günther, Thomas Eschbach, Lothar Linhard, Gerhard Angst
    Recursive Bi-Partitioning of Netlists for Large Number of Partitions. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:38-44 [Conf]
  11. Bernd Becker, Thomas Eschbach, Rolf Drechsler, Wolfgang Günther
    Greedy_IIP: Partitioning Large Graphs by Greedy Iterative Improvement. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:54-61 [Conf]
  12. Rolf Drechsler, Wolfgang Günther
    Generation of Optimal Universal Logic Modules. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1999, pp:1080-1085 [Conf]
  13. Rolf Drechsler, Wolfgang Günther, Bernd Becker
    Testability of Circuits Derived from Lattice Diagrams. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 2000, pp:1188-1192 [Conf]
  14. Wolfgang Günther, Rolf Drechsler
    ACTion: Combining Logic Synthesis and Technology Mapping for MUX Based FPGAs. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 2000, pp:1130-1137 [Conf]
  15. Wolfgang Günther, Nicole Drechsler, Rolf Drechsler, Bernd Becker
    Verification of Designs Containing Black Boxes. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 2000, pp:1100-1105 [Conf]
  16. Nicole Drechsler, Wolfgang Günther, Rolf Drechsler
    Efficient Graph Coloring by Evolutionary Algorithms. [Citation Graph (0, 0)][DBLP]
    Fuzzy Days, 1999, pp:30-39 [Conf]
  17. Thomas Eschbach, Wolfgang Günther, Rolf Drechsler, Bernd Becker
    Crossing Reduction by Windows Optimization. [Citation Graph (0, 0)][DBLP]
    Graph Drawing, 2002, pp:285-294 [Conf]
  18. Wolfgang Günther, Robby Schönfeld, Bernd Becker, Paul Molitor
    k-Layer Straightline Crossing Minimization by Speeding Up Sifting. [Citation Graph (0, 0)][DBLP]
    Graph Drawing, 2000, pp:253-258 [Conf]
  19. Rolf Drechsler, Wolfgang Günther
    Evolutionary Synthesis of Multiplexor Circuits under Hardware Constraints. [Citation Graph (0, 0)][DBLP]
    GECCO, 2000, pp:513-518 [Conf]
  20. Wolfgang Günther, Rolf Drechsler
    Improving EAs for Sequencing Problems. [Citation Graph (0, 0)][DBLP]
    GECCO, 2000, pp:175-180 [Conf]
  21. Stefan Geyer, Wolfgang Günther, Siegfried Paul
    Erfahrungen bei objektorientierter SW-Entwicklung für ein großes Prjekt: 10 Thesen. [Citation Graph (0, 0)][DBLP]
    GI Jahrestagung, 1993, pp:433-438 [Conf]
  22. Thomas Eschbach, Wolfgang Günther, Bernd Becker
    Orthogonal hypergraph routing for improved visibility. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:385-388 [Conf]
  23. Wolfgang Günther, Rolf Drechsler
    Linear Transformations and Exact Minimization of BDDs. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1998, pp:325-330 [Conf]
  24. Wolfgang Günther, Rolf Drechsler
    Efficient manipulation algorithms for linearly transformed BDDs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:50-54 [Conf]
  25. Wolfgang Günther, Rolf Drechsler, Stefan Höreth
    Efficient Dynamic Minimization of Word-Level DDs Based on Lower Bound Computation. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:383-388 [Conf]
  26. Rolf Drechsler, Wolfgang Günther
    History-Based Dynamic Minimization During BDD Construction. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:334-345 [Conf]
  27. Wolfgang Günther, Rolf Drechsler
    Minimization of BDDs using linear transformations based on evolutionary techniques. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:387-390 [Conf]
  28. Wolfgang Günther, Rolf Drechsler
    Creating hard problem instances in logic synthesis using exact minimization. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 1999, pp:436-439 [Conf]
  29. Dragan Jankovic, Wolfgang Günther, Rolf Drechsler
    Lower Bound Sifting for MDDs. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2000, pp:193-198 [Conf]
  30. Frank Schmiedle, Wolfgang Günther, Rolf Drechsler
    Dynamic Re-Encoding During MDD Minimization. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2000, pp:239-244 [Conf]
  31. Frank Schmiedle, Wolfgang Günther, Rolf Drechsler
    Selection of Efficient Re-Ordering Heuristics for MDD Construction. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2001, pp:299-304 [Conf]
  32. Mitchell A. Thornton, Rolf Drechsler, Wolfgang Günther
    A Method for Approximate Equivalence Checking. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2000, pp:447-452 [Conf]
  33. Thomas Eschbach, Wolfgang Günther, Bernd Becker
    Cross Reduction for Orthogonal Circuit Visualization. [Citation Graph (0, 0)][DBLP]
    VLSI, 2003, pp:107-113 [Conf]
  34. Thomas Eschbach, Wolfgang Günther, Bernd Becker
    Orthogonal Circuit Visualization Improved by Merging the Placement and Routing Phases. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:433-438 [Conf]
  35. Wolfgang Günther, Rolf Drechsler
    Implementation of Read- k-times BDDs on Top of Standard BDD Packages. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:173-178 [Conf]
  36. Wolfgang Günther, Rolf Drechsler
    Performance Driven Optimization for MUX based FPGAs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:311-316 [Conf]
  37. Wolfgang Günther, Jürgen F. H. Winkler
    Anwendung der Objektorientierung in einem industriellen Telekommunikationsprojekt. [Citation Graph (0, 0)][DBLP]
    Informatik Spektrum, 1993, v:16, n:6, pp:341-348 [Journal]
  38. Wolfgang Günther, Rolf Drechsler
    Minimization of free BDDs. [Citation Graph (0, 0)][DBLP]
    Integration, 2002, v:32, n:1-2, pp:41-59 [Journal]
  39. Rolf Drechsler, Wolfgang Günther
    History-based dynamic BDD minimization. [Citation Graph (0, 0)][DBLP]
    Integration, 2001, v:31, n:1, pp:51-63 [Journal]
  40. Rolf Drechsler, Wolfgang Günther, Stefan Höreth
    Minimization of Word-Level Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    Integration, 2002, v:33, n:1-2, pp:39-70 [Journal]
  41. Ilia Polian, Wolfgang Günther, Bernd Becker
    Pattern-based verification of connections to intellectual property cores. [Citation Graph (0, 0)][DBLP]
    Integration, 2003, v:35, n:1, pp:25-44 [Journal]
  42. Wolfgang Günther, Rolf Drechsler
    On the computational power of linearly transformed BDDs. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 2000, v:75, n:3, pp:119-125 [Journal]
  43. Rolf Drechsler, Wolfgang Günther, Thomas Eschbach, Lothar Linhard, Gerhard Angst
    Recursive bi-partitioning of netlists for large number of partitions. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2003, v:49, n:12-15, pp:521-528 [Journal]
  44. Wolfgang Günther, Rolf Drechsler
    Efficient Minimization and Manipulation of Linearly Transformed Binary Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:9, pp:1196-1209 [Journal]
  45. Rolf Drechsler, Nicole Drechsler, Wolfgang Günther
    Fast exact minimization of BDD's. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:3, pp:384-389 [Journal]
  46. Rolf Drechsler, Wolfgang Günther, Fabio Somenzi
    Using lower bounds during dynamic BDD minimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:1, pp:51-57 [Journal]
  47. Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler
    An improved branch and bound algorithm for exact BDD minimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:12, pp:1657-1663 [Journal]
  48. Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler
    Combining ordered best-first search with branch and bound for exact BDD minimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:10, pp:1515-1529 [Journal]

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