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Publications of Author

1. Hisakazu Edamatsu, Katsumi Homma, Masaru Kakimoto, Yutaka Koike, Kinya Tabuchi
   Pre-layout Delay Calculation Specification for CMOS ASIC Libraries. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 1998, pp:241-248 [Conf]
   
2. 
   Efficiently finding the 'best' solution with multi-objectives from multiple topologies in topology library of analog circuit. [Citation Graph (, )][DBLP]
   
   
3. 
   Non-Gaussian Statistical Timing models of die-to-die and within-die parameter variations for full chip analysis. [Citation Graph (, )][DBLP]
   
   
4. 
   Generation of yield-embedded Pareto-front for simultaneous optimization of yield and performances. [Citation Graph (, )][DBLP]